Abstract: A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control request signal, the chipset turns off the input buffer.

Abstract: In a computer system including a central processing unit, a system memory, a south bridge module, a north bridge module and multiple hard disk drives, a RAID control function is exhibited. The method includes steps of: issuing a command addressing to the south bridge module by the central processing unit; and performing a fault-tolerant computing operation in the north bridge module while exempting from transmitting the command to the south bridge module when the command contains a specified address data.

Abstract: A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control request signal, the chipset turns off the input buffer.

Abstract: RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data. The timing for performing the fault-tolerant data computing operation is determined by accessing a data stored in one of the hard disk drives, detecting a partial data length of a data stream having been transmitted from the hard disk drive to the computer system, issuing a triggering signal when the data length has reached a unitary length less than the total length of the data stream, and then performing the fault-tolerant data computing operation with the unitary length of data in response to the triggering signal.

Abstract: A bi-stable display having a plurality of bi-stable light emitting diodes (LEDs) and a driver are provided. The bi-stable LEDs have bi-stable memory characteristics and emit light according to a plurality of specified voltages, wherein the driver is used to apply the specified voltages to the bi-stable LEDs. The driver further has a brightness controller. The brightness controller is used to control the brightness of the bi-stable display by controlling a plurality of durations in which the specified voltages are applied to the bi-stable LEDs for a plurality of frames.

Abstract: A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Abstract: A method of power management of a CPU connects to a plurality of host bridges. The method is applied to a CPU connecting to the host bridges. When the host bridges are detected as no bus master signal being received, a command is transmitted to force the host bridges not to transmit the bus master signal to the CPU when they receive the bus master signal. After the CPU enters the C3 state, if the host bridges are detected that any one of the host bridges receives the bus master signal, the CPU is forced to quit the C3 state, and the host bridges are forced to transmit the bus master signal to the CPU.

Abstract: A power management device for multiprocessor systems and method thereof applied to force individual processor entering or leaving of a C3 state are disclosed. The device includes at least one checking unit, a plurality of recording units and a plurality of arbiters. The checking unit receives an event from a peripheral device, checks which processor the event corresponds and sends a checking signal. The event is received and recorded by one of the recording units according to the checking signal. Once the recording unit has no record of the received event, the corresponding processor turns the corresponding arbiter off and sends an entering C3 state command. A first control signal is sent to the processor according to the entering C3 state command so as to force the processor into the C3 state.

Abstract: A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot reset packet cannot be executed by the high-speed PCI device, the host controller chipset can respectively transmit a trigger signal and a PCI reset signal to each corresponding reset signal generator through a trigger signal line and a PCI reset signal line, and further the reset signal generator operates to generate a basic resetting signal. Finally, the basic resetting signal will be transmitted to the corresponding high-speed PCI device through a basic reset signal line such that the system can be used to operate the basic resetting action without restarting power.

Abstract: The present invention relates to a method for configuring a Peripheral Component Interconnect Express (PCIE). A plurality of PCIE parameters are stored in a storage unit. When a computer system starts up, a North Bridge chip is driven to read the PCIE parameters in the storage unit for configuring the PCIE. According to the configuration method of the present invention, when the computer system starts up, the North Bridge chip and the storage unit are enabled first. Then, the North Bridge chip is driven to read the PCIE parameters. Finally, the North Bridge chip proceeds with initialization according to the PCIE parameters to configure PCIE.

Abstract: A control device and method are used for adjusting the refresh rate of a memory module in a computer system. The device includes a thermo sensor and a control circuit. In the control method, the thermo sensor actively outputs a temperature change signal in response to the temperature change in the memory module when a capacitor of the memory module incurs an aggravated current leakage due to the temperature rise. Next, the control circuit adjusts the refresh rate in response to the temperature change signal and refreshes the memory module at the refresh rate.

Abstract: A power-on method for a computer system comprising a processor supporting Hyper-Threading, a Read Only Memory (ROM) and a main memory, wherein the processor comprises a cache memory and the ROM comprises BIOS codes. The power-on method comprises the following steps. First, the processor is initialized in a Hyper-Threading disabled mode. The BIOS codes is then copied from the ROM to the cache memory, and the main memory is initialized by executing the BIOS codes therein. Thereafter, the processor is re-initialized in a Hyper-Threading enabled mode after the main memory is initialized. The processor comprises a first logic unit and a second logic unit. When initializing the processor, a first potential is applied to pin A31 of the processor, and a reset signal is delivered to the processor while the pin A31 is at the first potential, such that the processor is initialized in the Hyper-Threading disabled mode.

Abstract: A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP bus. The second bridge is electrically connected between the first AGP bus and the PCI bus. The controller is electrically connected to the first AGP bus, the first bridge, and the second bridge. As a configuration cycle corresponding to the first bridge being transmitted through the first AGP bus to the controller, the controller responds a preset message implying that the first bridge does not exist.

Abstract: A device for burst reading/writing memory data includes a memory module and a north bridge chipset. The device is used for executing a power on self test (POST). The memory module has a plurality of memory cells and the north bridge chipset includes a programmable register module and a memory module controller, wherein the programmable register module stores at least one set of default information. The memory module controller performing burst read/write on the memory cells according to the default information stored in the programmable register module.

Abstract: A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Abstract: A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Abstract: A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.

Abstract: RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data.

Abstract: In a computer system including a central processing unit, a system memory, a south bridge module, a north bridge module and multiple hard disk drives, a RAID control function is exhibited. The method includes steps of: issuing a command addressing to the south bridge module by the central processing unit; and performing a fault-tolerant computing operation in the north bridge module while exempting from transmitting the command to the south bridge module when the command contains a specified address data.

Abstract: A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.