Patents by Inventor Kuan-Liang Liu
Kuan-Liang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10903334Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: GrantFiled: March 10, 2020Date of Patent: January 26, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Publication number: 20210005558Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.Type: ApplicationFiled: September 24, 2020Publication date: January 7, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ming WU, Kuan-Liang LIU, Pao-Tung CHEN
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Publication number: 20200402857Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Applicant: United Microelectronics Corp.Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
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Publication number: 20200350302Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Wen-De Wang, Yung-Lung Lin
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Patent number: 10796964Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.Type: GrantFiled: May 31, 2019Date of Patent: October 6, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
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Patent number: 10790240Abstract: A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.Type: GrantFiled: March 17, 2017Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
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Patent number: 10781098Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer; receiving a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; and bonding the first conductive structure with the second conductive structure.Type: GrantFiled: May 6, 2019Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hung-Hua Lin, Ping-Yin Liu, Kuan-Liang Liu, Chia-Shiung Tsai, Alexander Kalnitsky
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Patent number: 10727218Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.Type: GrantFiled: November 27, 2018Date of Patent: July 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Wen-De Wang, Yung-Lung Lin
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Publication number: 20200231845Abstract: The present invention provides a light detectable thermal-release pressure-sensitive adhesive and an application thereof. Heat-expandable foaming particles are added to a formula of the light detectable thermal-release pressure-sensitive adhesive, so that the product has high adhesion; moreover, after curing and molding, the adhesion can be greatly reduced by a heating process, so the problem that the existing high-adhesion pressure-sensitive adhesive film is not torn easily is solved; and meanwhile, by adding an inorganic fluorescent material, the light detectable thermal-release pressure-sensitive adhesive absorbs ultraviolet light and then can emit a visible wavelength to detect adhesive residues quickly; and by applying the light detectable thermal-release pressure-sensitive adhesive to a manufacture procedure, the adhesive residues are not occurred easily and thus the convenience of detecting the adhesive residue is increased.Type: ApplicationFiled: May 15, 2019Publication date: July 23, 2020Inventors: YI-CHEN YANG, KUAN-LIANG LIU
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Publication number: 20200212201Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: ApplicationFiled: March 10, 2020Publication date: July 2, 2020Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Publication number: 20200135541Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.Type: ApplicationFiled: January 2, 2020Publication date: April 30, 2020Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
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Patent number: 10629697Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: GrantFiled: November 15, 2016Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Publication number: 20200051950Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Xin-Hua Huang, Kuan-Liang Liu, Kuo Liang Lu, Ping-Yin Liu
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Patent number: 10553474Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.Type: GrantFiled: September 24, 2018Date of Patent: February 4, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
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Patent number: 10497667Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.Type: GrantFiled: March 26, 2018Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xin-Hua Huang, Kuan-Liang Liu, Kuo Liang Lu, Ping-Yin Liu
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Patent number: 10453832Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.Type: GrantFiled: August 1, 2017Date of Patent: October 22, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Wen-De Wang, Yung-Lung Lin
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Publication number: 20190287860Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.Type: ApplicationFiled: May 31, 2019Publication date: September 19, 2019Applicant: United Microelectronics Corp.Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu
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Publication number: 20190256352Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer; receiving a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; and bonding the first conductive structure with the second conductive structure.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: HUNG-HUA LIN, PING-YIN LIU, KUAN-LIANG LIU, CHIA-SHIUNG TSAI, ALEXANDER KALNITSKY
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Patent number: 10373876Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.Type: GrantFiled: April 16, 2018Date of Patent: August 6, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu
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Patent number: 10373872Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.Type: GrantFiled: November 15, 2017Date of Patent: August 6, 2019Assignee: United Microelectronics Corp.Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Kuan-Liang Liu