Patents by Inventor Kuan Lin Chen

Kuan Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154043
    Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240145520
    Abstract: The present disclosure provides a method for fabricating an image sensor. The method includes the following operations. A cavity is formed at a first surface of a substrate. A germanium layer is formed in the cavity. A first heavily doped region is formed in the germanium layer by an implantation operation. A second heavily doped region is formed at a position proximal to a top surface of the germanium layer, wherein the second heavily doped region is laterally surrounded by the first heavily doped region from a top view perspective. An interconnect structure is formed over the germanium layer.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: JHY-JYI SZE, SIN-YI JIANG, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, KUAN-CHIEH HUANG, JUNG-I LIN
  • Publication number: 20240144394
    Abstract: A Method implemented by a display system for hosting digital content team display contests and quantifying social media popularity, is implemented through a display system. The system consists of a display server and a user big data server. The method involves multiple users participating in a display team, where the display server showcases the digital content contributed by these users as showpiece. Furthermore, the display server displays the showpiece and/or the display team in a display theme and records the social media interaction behavior data of the showpiece and/or the display team, which is then transmitted to the user big data server. The user big data server calculates the social media interaction behavior data of the showpiece and/or the team based on the quality differences in social media interaction behaviors and stores them separately in a database. Users can increase the popularity and value of their created digital content by participating in the display team.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 2, 2024
    Inventors: Kuan Yu CHEN, You Lin YAO
  • Publication number: 20240136401
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.
    Type: Application
    Filed: January 5, 2024
    Publication date: April 25, 2024
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20240136484
    Abstract: An electronic device includes a substrate, a semiconductor unit and an insulating layer. The semiconductor unit is disposed on the substrate. The insulating layer is disposed on the semiconductor unit, and the insulating layer includes a first portion and a second portion connected to the first portion. In a top view, the first portion partially overlaps the semiconductor unit, the second portion does not overlap the semiconductor unit, and a part of an edge of the insulating layer is irregular.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Applicant: InnoLux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
  • Publication number: 20240136299
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20240123151
    Abstract: An insertion device includes an upper casing, an insertion module and a lower casing. The insertion module is disposed in the upper casing, and includes a main body assembly, an insertion seat, a first elastic member, a retraction seat and a second elastic member. When the upper casing is depressed, the insertion seat is driven by the first elastic member to perform an automatic-insertion operation, such that limiting structure between the insertion seat and the retraction seat collapses upon the collapse of another limiting structure between the insertion seat and the main body assembly, and that the retraction seat is driven by the second elastic member to perform an automatic-retraction operation.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Chen-Hao Lee, Kuan-Lin Chang
  • Publication number: 20240120451
    Abstract: An electronic assembly is provided. The electronic assembly includes a first circuit structure including a conductive structure, a second circuit structure disposed on the first circuit structure, a plurality of electronic elements disposed on the first circuit structure, and a connecting element disposed on the first circuit layer. The connecting element is disposed between two adjacent ones of the plurality electronic elements and electrically connected to the second circuit layer and one of the two adjacent ones of the plurality of electronic elements.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Jia-Yuan CHEN, Tsung-Han TSAI, Kuan-Feng LEE, Yuan-Lin WU
  • Patent number: 11952656
    Abstract: A physical vapor deposition (PVD) system is disclosed. The PVD system includes a pedestal configured to hold a semiconductor wafer, a cover plate configured to hold a target, and a collimator between the pedestal and the cover plate. The collimator includes a plurality of passages configured to pass source material travelling from the cover plate toward the pedestal at an angle less than a threshold angle with respect to a line perpendicular to a surface of the pedestal facing the cover plate, where the collimator is configured to block source material travelling from the cover plate toward the pedestal at an angle greater than the threshold angle, where a first passage of the plurality of passages has a first passage length, where a second passage of the plurality of passages has a second passage length, and where the first passage length is less than the second passage length.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Chen, Tsung-Yi Chou, Wei-Der Sun, Hao-Wei Kang
  • Publication number: 20240105877
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Publication number: 20240096942
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20240090838
    Abstract: A physiological signal monitoring device includes a base, a sensor, a transmitter, an adhesive layer and a pad. The sensor is carried by the base. The transmitter is coupled to the sensor. The adhesive layer is arranged on a bottom surface of the base. The pad includes an adhesive backing and a coupling backing. The adhesive backing is fabricated by weaving first threads and includes first holes. The coupling backing provides a coupling surface, and is fabricated by weaving second threads and includes second holes and piques. The piques are arranged on the coupling surface to form convex and concave three-dimensional textures on the coupling surface. The adhesive layer soaks the pad through the second holes and wraps at least one of the second threads and the first threads, so as to make the pad be connected to the base through the adhesive layer.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 21, 2024
    Inventors: Chieh-Hsing CHEN, Kuan-Lin CHANG
  • Patent number: 11935795
    Abstract: Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Wang, Tsung-Lin Lee, Wen-Chih Chiang, Kuan-Jung Chen
  • Patent number: 11925789
    Abstract: An elastic physiological patch includes a patch assembly and an implant assembly. The patch assembly includes an electronic device, and a soft patch body defining a chamber for receiving the electronic device. The implant assembly is mountable to the electronic device and includes an implant which is capable of being driven to partially pass through the patch body and which is adapted to be implanted in the skin of a subject. The implant and the patch body cooperatively seal the chamber.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: March 12, 2024
    Assignee: Bionime Corporation
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Jia-Nan Shen, Kuan-Lin Chang
  • Patent number: 11889645
    Abstract: A foldable electronic device includes a first casing, a second casing, a hinge structure and a foldable display. The hinge structure connects the first casing and the second casing, and includes a plurality of supporting blocks, a plurality of first hinge blocks and a plurality of second hinge blocks. The supporting blocks are arranged side by side between the first casing and the second casing. The first hinge blocks and the second hinge blocks are respectively arranged at two sides of the supporting blocks. One of the first hinge blocks connects two of the supporting blocks adjacent to each other. One of the second hinge blocks connects two of the supporting blocks adjacent to each other. The foldable display includes a first bonding portion secured to the first casing, a second bonding portion secured to the second casing and a foldable portion aligned to the hinge structure.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: January 30, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Ping Sun, Wei-Chih Wang, Chun-Hung Wen, Yu-Cheng Shih, Yen-Chou Chueh, Chi-Tai Ho, Kuan-Lin Chen, Chun-Hsien Chen, Chih-Heng Tsou
  • Publication number: 20230413073
    Abstract: Apparatus and methods are provided for determining AR filter coefficient and numbers of synchronization. In one novel aspect, the AR filter coefficient and times of synchronization are determined based on the temperatures of the oscillator. In one embodiment, the UE determines a temperature drift rate by collecting sets of temperatures before and after the UE in the sleep mode of the CDRX, generates one or more threshold look-up tables and performs an optimization selection based on the temperature drift rate and the one or more threshold of look-up tables, wherein the optimization selection comprising selecting an alpha coefficient and a number of subframes for synchronization. In another embodiment, the optimization selection is further determined based on a subcarrier spacing, and a channel type of being a static channel type and a fading channel type. The UE further performs an on-the-fly oscillator S-curve calibration based on the set of temperatures.
    Type: Application
    Filed: June 17, 2023
    Publication date: December 21, 2023
    Inventors: YUAN YUAN, Jianwei Zhang, Jun Hu, Nien-En Wu, PENG YANG, Kuan-Lin Chen, Yen-Chen Chen, Cheng-Yu Tsai, Zhi Zheng
  • Patent number: 11849283
    Abstract: A method and system or device such as a hearing aid are provided for processing audio signals. In accordance with the method, an audio signal is received and divided into a plurality of frequency sub-bands. For each of the frequency sub-band signals, the signal is further divided into overlapping temporal frames. Each of the temporal frames are windowed. Frequency warping is performed on each of the windowed frames. Overlap-and-add is performed on the frequency warped frames. The frequency warped sub-bands are combined into a full band to provide a frequency warped signal.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: December 19, 2023
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Harinath Garudadri, Ching-Hua Lee, Kuan-Lin Chen, Fred Harris, Bhaskar Rao
  • Publication number: 20230354554
    Abstract: A heat dissipation system suitable for a portable electronic device with two heat sources is provided. The heat dissipation system includes a fan, two heat dissipation fin sets, a gate, a first heat pipe, a second heat pipe, and a control unit. The fan is a centrifugal fan and has a main outlet and a sub outlet. The heat dissipation fin sets are disposed respectively at the main outlet and the sub outlet, and the gate is disposed at the sub outlet. The first heat pipe thermally contacts the heat sources and the heat dissipation fin set located at the main outlet. The second heat pipe thermally contacts one of the heat sources and the two heat dissipation fin sets. The control unit is electrically connected to the gate to drive the gate to open or close the sub outlet according to a load of the two heat sources.
    Type: Application
    Filed: April 25, 2023
    Publication date: November 2, 2023
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Tsung-Ting Chen, Jau-Han Ke, Chun-Chieh Wang, Chi-Tai Ho, Kuan-Lin Chen
  • Publication number: 20230282010
    Abstract: The present application discloses a method for detecting image by using semantic segmentation. To input an image with data augmentation, and then encode and decode using a neural network. At least one semantically divided, and finally the at least one semantically divided is compared with the sample to classify as a target or a non-target. In this way, the CNN is used to detect whether the image is the SCC image or not, and locate the section, thereby assisting the doctor in interpreting the esophagus image.
    Type: Application
    Filed: January 31, 2023
    Publication date: September 7, 2023
    Inventors: HSIANG-CHEN WANG, KUAN-LIN CHEN, YU-MING TSAO, JEN-FENG HSU
  • Publication number: 20230060047
    Abstract: A physical vapor deposition (PVD) system is disclosed. The PVD system includes a pedestal configured to hold a semiconductor wafer, a cover plate configured to hold a target, and a collimator between the pedestal and the cover plate. The collimator includes a plurality of passages configured to pass source material travelling from the cover plate toward the pedestal at an angle less than a threshold angle with respect to a line perpendicular to a surface of the pedestal facing the cover plate, where the collimator is configured to block source material travelling from the cover plate toward the pedestal at an angle greater than the threshold angle, where a first passage of the plurality of passages has a first passage length, where a second passage of the plurality of passages has a second passage length, and where the first passage length is less than the second passage length.
    Type: Application
    Filed: March 22, 2022
    Publication date: February 23, 2023
    Inventors: Kuan-Lin Chen, Tsung-Yi Chou, Wei-Der Sun, Hao-Wei Kang