Patents by Inventor Kuan-Lun Cheng

Kuan-Lun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971609
    Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang, Kuan-Lun Cheng
  • Publication number: 20210098450
    Abstract: The present disclosure describes a method to form a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wang-Chun Huang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20210098625
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG, Min CAO, Jung-Hung CHANG, Lo-Heng CHANG, Pei-Hsun WANG, Kuo-Cheng CHIANG
  • Publication number: 20210098618
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 1, 2021
    Inventors: Chi-Hsing Hsu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Sai-Hooi Yeong
  • Patent number: 10964816
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20210066469
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.
    Type: Application
    Filed: June 8, 2020
    Publication date: March 4, 2021
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210066291
    Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung LIN, Yi-Hsun CHIU, Shang-Wen CHANG, Ching-Wei TSAI, Yu-Xuan HUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20210057541
    Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first fin structure and a second fin structure. The method further includes replacing the second fin structure with a third fin structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first fin structure and the second sacrificial layers in the third fin structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first fin structure and each of the second semiconductor layers in the third fin structure, respectively.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wang-Chun Huang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20210057559
    Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang, Kuan-Lun Cheng
  • Publication number: 20210043751
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sai-Hooi YEONG, Chi-On CHUI, Bo-Feng YOUNG, Bo-Yu LAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20210035870
    Abstract: A semiconductor device is provided. The device includes a first pair and a second pair of source/drain features over a semiconductor substrate. The first pair of source/drain features are p-type doped. The second pair of source/drain features are n-type doped. A first stack of semiconductor layers connect the first pair of source/drain features along a first direction. A second stack of semiconductor layers connect the second pair of source/drain features along a second direction. A first gate is between vertically adjacent layers of the first stack of semiconductor layers. The first gate has a first portion that has a first dimension along the first direction. A second gate is between vertically adjacent layers of the second stack of semiconductor layers. The second gate has a second portion that has a second dimension along the second direction. The second dimension is larger than the first dimension.
    Type: Application
    Filed: May 15, 2020
    Publication date: February 4, 2021
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10868182
    Abstract: A field effect transistor (FET) including a substrate, a plurality of insulators, a gate stack, a first strained material, a second strained material, a first conducive via, a second conductive via, and a silicide layer. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are in the trenches. The gate stack is disposed over the semiconductor fins and on the insulators. The first strained material is located on one side of the gate stack and the second strained material is located on another side of the gate stack. The first conductive via is electrically connected to the first strained material and the second conductive via is electrically connected to the second strained material. The silicide layer contacts the first strained material and the first conductive via and contacts the second strained material and the second conductive via.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10861973
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hsing Hsu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Sai-Hooi Yeong
  • Patent number: 10861958
    Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Lun Cheng, Li-Shyue Lai, Ching-Wei Tsai, Kai-Chieh Yang
  • Publication number: 20200365707
    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-K gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Yi CHUANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 10833167
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Chi-On Chui, Bo-Feng Young, Bo-Yu Lai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200301118
    Abstract: A light path adjustment mechanism includes a bracket, a light valve, a carrier, a first axis, a second axis and an optical plate member. A surface normal of a surface of the light valve crosses the bracket to define an intersection closest to the surface of the light valve, and the bracket has an end point furthest from the intersection measured in the direction of the surface normal. A distance between the intersection and the surface measured in the direction of the surface normal is smaller than a distance between the intersection and the end point measured in the direction of the surface normal.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 24, 2020
    Inventors: WEI-SZU LIN, Yu-Chen CHANG, CHIH-CHIEN LIN, YU-TING CHENG, KUAN-LUN CHENG
  • Publication number: 20200279853
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming an shallow trench isolation (STI) structure on the substrate and between the first semiconductor fin and the second semiconductor fin; forming a spacer layer on the first semiconductor fin, the second semiconductor fin, and the STI structure; patterning the spacer layer to form a spacer extending along the second sidewall of the first semiconductor fin, a top surface of the STI structure, and the second sidewall of the second semiconductor fin; forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tetsu OHTOU, Ching-Wei TSAI, Kuan-Lun CHENG, Yasutoshi OKUNO, Jiun-Jia HUANG
  • Publication number: 20200176590
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, an insulator fin over the semiconductor substrate, the insulator fin having a principle dimension, from a cross sectional perspective, perpendicular to a top surface of the semiconductor substrate, and a semiconductor capping layer cover the insulator fin along the principle dimension. A method for manufacturing a semiconductor structure is also disclosed in the present disclosure.
    Type: Application
    Filed: June 19, 2019
    Publication date: June 4, 2020
    Inventors: CHI-YI CHUANG, CHING-WEI TSAI, KUAN-LUN CHENG, CHIH-HAO WANG
  • Publication number: 20200176326
    Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.
    Type: Application
    Filed: July 8, 2019
    Publication date: June 4, 2020
    Inventors: Yi-Bo Liao, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng