Patents by Inventor Kuan-Neng Chen
Kuan-Neng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030184Abstract: An embodiment of the present application provides a semiconductor device, including a substrate, a chip, a latch-up protection circuit, and a redistribution layer. The chip is on the substrate. The latch-up protection circuit is separated from the chip in a direction. The redistribution layer transmits a signal between the latch-up protection circuit and the chip.Type: ApplicationFiled: December 7, 2022Publication date: January 25, 2024Inventors: Kuan-Neng CHEN, Yi-Chieh TSAI, Demin LIU, Han-Wen HU
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Publication number: 20230411388Abstract: An IC structure includes a first transistor, a dielectric layer, a plurality of semiconductor pillars, a plurality of semiconductor plugs, a semiconductor structure, and a second transistor. The first transistor is formed on a substrate. The dielectric layer is above the first transistor. The semiconductor pillars extend from the substrate into the dielectric layer. The semiconductor plugs extend from a top surface of the dielectric layer into the dielectric layer to the plurality of semiconductor pillars. The semiconductor structure is disposed over the top surface of the dielectric layer. The second transistor is formed on the semiconductor structure.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung UniversityInventors: Chenming HU, Kuan-Neng CHEN, Po-Tsang HUANG, Hao-Tung CHUNG, Bo-Jheng SHIH, Yu-Ming PAN
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Publication number: 20230402744Abstract: An antenna package structure is provided. The antenna package structure includes a glass substrate, an interconnect structure, a plurality of semiconductor chips, and an antenna array structure. The glass substrate has a first surface and a second surface opposite to the first surface. The interconnect structure is disposed over the first surface of the glass substrate. The plurality of semiconductor chips are mounted over the interconnect structure. The antenna array structure is formed on the second surface of the glass substrate. Furthermore, the plurality of semiconductor chips are coupled to the antenna array structure through the interconnect structure and the glass substrate.Type: ApplicationFiled: December 14, 2022Publication date: December 14, 2023Inventors: KUAN-NENG CHEN, HAN-WEN HU, YI-CHIEH TSAI, YU-JIU WANG, LI HAN CHANG
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Patent number: 11621241Abstract: A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.Type: GrantFiled: September 17, 2021Date of Patent: April 4, 2023Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Han-Wen Hu, Demin Liu, Yi-Chieh Tsai, Kuan-Neng Chen
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Publication number: 20230025936Abstract: A bonding element and a method for manufacturing the same thereof are provide, wherein the method comprises the following steps: providing a carrier substrate; forming a first metal layer on the carrier substrate; forming a first insulating layer on the first metal layer, wherein the first insulating layer includes a first through hole; forming a first passivation layer and a first conductive layer in the first through hole, wherein the first passivation layer and the first conductive layer in the first through hole form a first connecting bump; forming a first substrate on the first connection bump and the first insulating layer; removing the carrier substrate and the first metal layer to form a first sub-bonding element; and connecting the first sub-bonding element and a second sub-bonding element with a surface of the first passivation of the first connection bump to form the bonding element.Type: ApplicationFiled: September 17, 2021Publication date: January 26, 2023Inventors: Han-Wen HU, Demin LIU, Yi-Chieh TSAI, Kuan-Neng CHEN
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Patent number: 9984993Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.Type: GrantFiled: October 14, 2016Date of Patent: May 29, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Min-Fong Shu, Yi-Hsiu Tseng, Kuan-Neng Chen, Shu-Chiao Kuo
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Patent number: 9931813Abstract: A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.Type: GrantFiled: May 6, 2010Date of Patent: April 3, 2018Assignee: Industrial Technology Research InstituteInventors: Kuan-Neng Chen, Wei-Chung Lo, Cheng-Ta Ko
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Publication number: 20170033075Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.Type: ApplicationFiled: October 14, 2016Publication date: February 2, 2017Inventors: Min-Fong SHU, Yi-Hsiu TSENG, Kuan-Neng CHEN, Shu-Chiao KUO
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Patent number: 9496238Abstract: A bonding structure includes a substrate having a top surface and including at least one bonding pad. Each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface. A semiconductor element includes at least one pillar. Each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.Type: GrantFiled: February 13, 2015Date of Patent: November 15, 2016Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Min-Fong Shu, Yi-Hsiu Tseng, Kuan-Neng Chen, Shu-Chiao Kuo
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Publication number: 20160240503Abstract: The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding structure comprises a substrate, having a top surface and including at least one bonding pad, wherein each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface; and a semiconductor element including at least one pillar, wherein each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Min-Fong Shu, Yi-Hsiu TSENG, Kuan-Neng CHEN, Shu-Chiao KUO
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Patent number: 9373564Abstract: A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided.Type: GrantFiled: March 6, 2015Date of Patent: June 21, 2016Assignee: Industrial Technology Research InstituteInventors: Wen-Wei Shen, Kuan-Neng Chen, Cheng-Ta Ko
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Publication number: 20160043018Abstract: A semiconductor device includes a substrate, a redistribution layer, a plurality of through-silicon vias (TSVs), and a plating seed layer. The substrate has a first surface and a second surface opposite to each other, and a plurality of cavities. The redistribution layer is disposed on the first surface, and the TSVs are respectively disposed in the cavities. The plating seed layer is disposed between the inner wall of each of the cavities and the corresponding TSVs. The anti-oxidation layer is disposed between the plating seed layer and the corresponding TSVs. The buffer layer covers the first surface and exposes the redistribution layers. Furthermore, a manufacturing method and a stacking structure of the semiconductor device are also provided.Type: ApplicationFiled: March 6, 2015Publication date: February 11, 2016Inventors: Wen-Wei Shen, Kuan-Neng Chen, Cheng-Ta Ko
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Patent number: 9196595Abstract: The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.Type: GrantFiled: February 27, 2014Date of Patent: November 24, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kuo-Hua Chen, Tzu-Hua Lin, Kuan-Neng Chen, Yan-Pin Huang
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Patent number: 8951837Abstract: A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.Type: GrantFiled: September 6, 2012Date of Patent: February 10, 2015Assignee: National Chiao Tung UniversityInventors: Kuan-Neng Chen, Yao-Jen Chang
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Publication number: 20150035165Abstract: An interconnection structure of a semiconductor device is provided, where the interconnection structure is constructed in a semiconductor substrate. The interconnection structure includes a first through silicon via and a second through silicon via both penetrating the semiconductor substrate, and the first through silicon via is spaced from the second through silicon via by a distance ranged from 2 ?m to 40 ?m.Type: ApplicationFiled: November 22, 2013Publication date: February 5, 2015Applicant: National Chiao Tung UniversityInventors: Kuan-Neng Chen, Yao-Jen Chang
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Patent number: 8927087Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate.Type: GrantFiled: September 17, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, Cornelia K. Tsang
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Patent number: 8900918Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.Type: GrantFiled: May 2, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, Yu-Ming Lin
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Patent number: 8878193Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.Type: GrantFiled: May 2, 2013Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, Yu-Ming Lin
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Publication number: 20140239494Abstract: The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.Type: ApplicationFiled: February 27, 2014Publication date: August 28, 2014Inventors: Kuo-Hua CHEN, Tzu-Hua LIN, Kuan-Neng CHEN, Yan-Pin HUANG
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Patent number: 8766734Abstract: The present invention provides a TSV-based oscillator WLP structure and a method for fabricating the same. The method of the present invention comprises steps: providing a silicon base having an oscillator unit disposed thereon; forming on the silicon base at least one package ring surrounding the oscillator unit; and disposing a silicon cap on the package ring to envelop the oscillator unit. The present invention adopts a cap and a base, which are made of the same material, to effectively overcome the problem of thermal stress occurring in a conventional sandwich package structure. Further, the present invention elaborately designs the wiring on the lower surface of the base to reduce the package size and decrease consumption of noble metals.Type: GrantFiled: June 22, 2012Date of Patent: July 1, 2014Assignee: TXC CorporationInventors: Chi-Chung Chang, Chih-Hung Chiu, Yen-Chi Chen, Kuan-Neng Chen, Jian-Yu Shih