Abstract: The present invention provides a TSV-based oscillator WLP structure and a method for fabricating the same. The method of the present invention comprises steps: providing a silicon base having an oscillator unit disposed thereon; forming on the silicon base at least one package ring surrounding the oscillator unit; and disposing a silicon cap on the package ring to envelop the oscillator unit. The present invention adopts a cap and a base, which are made of the same material, to effectively overcome the problem of thermal stress occurring in a conventional sandwich package structure. Further, the present invention elaborately designs the wiring on the lower surface of the base to reduce the package size and decrease consumption of noble metals.

Abstract: A three-dimensional integrated circuit, including a first adhesive bonding layer, a first chip, a second chip, and an inter-stratum thermal pad, is provided. The first adhesive bonding layer has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the first adhesive bonding layer. The first chip includes a hot zone. The second chip is disposed on the second surface of the first adhesive bonding layer. The inter-stratum thermal pad is embedded in the first adhesive bonding layer and faces to the hot zone.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate.

Abstract: A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Abstract: Copper (Cu)-to-Cu bonding techniques are provided. In one aspect, a bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one copper pad embedded in a first insulator and at least one via in the first insulator over the copper pad, wherein the via has tapered sidewalls. A second bonding structure is provided having at least one copper stud embedded in a second insulator, wherein a portion of the copper stud is exposed for bonding and has a domed shape. The first bonding structure is bonded to the second bonding structure by way of a copper-to-copper bonding between the copper pad and the copper stud, wherein the via and the copper stud fit together like a lock-and-key. A bonded structure is also provided.

Abstract: An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.

Abstract: A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher than the melting points of the top and bottom metal layers. The top and bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

Abstract: A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

Abstract: Copper (Cu)-to-Cu bonding techniques are provided. In one aspect, a bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one copper pad embedded in a first insulator and at least one via in the first insulator over the copper pad, wherein the via has tapered sidewalls. A second bonding structure is provided having at least one copper stud embedded in a second insulator, wherein a portion of the copper stud is exposed for bonding and has a domed shape. The first bonding structure is bonded to the second bonding structure by way of a copper-to-copper bonding between the copper pad and the copper stud, wherein the via and the copper stud fit together like a lock-and-key. A bonded structure is also provided.

Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

Abstract: The present invention provides a TSV-based oscillator WLP structure and a method for fabricating the same. The method of the present invention comprises steps: providing a silicon base having an oscillator unit disposed thereon; forming on the silicon base at least one package ring surrounding the oscillator unit; and disposing a silicon cap on the package ring to envelop the oscillator unit. The present invention adopts a cap and a base, which are made of the same material, to effectively overcome the problem of thermal stress occurring in a conventional sandwich package structure. Further, the present invention elaborately designs the wiring on the lower surface of the base to reduce the package size and decrease consumption of noble metals.

Abstract: A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: A device comprises a heater, a dielectric layer, a phase-change element, and a capping layer. The dielectric layer is disposed at least partially on the heater and defines an opening having a lower portion and an upper portion. The phase-change element occupies the lower portion of the opening and is in thermal contact with the heater. The capping layer overlies the phase-change element and occupies the upper portion of the opening. At least a fraction of the phase-change element is operative to change between lower and higher electrical resistance states in response to an application of an electrical signal to the heater.

Abstract: The present invention discloses a bonding method for a three-dimensional integrated circuit and the three-dimensional integrated circuit thereof. The bonding method comprises the steps of: providing a substrate; depositing a film layer on the substrate; providing a light source to light onto the film layer to form a graphic structure; forming a metal co-deposition layer by a first metal and a second metal that are co-deposited on the film layer; providing a first integrated circuit having the substrate, the film layer and the metal co-deposition layer sequentially; providing a second integrated circuit that having the metal co-deposition layer, the film layer and the substrate sequentially; and the first integrated circuit is bonded with the second integrated circuit at a predetermined temperature to form a three-dimensional integrated circuit.

Abstract: An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.