Patents by Inventor KUAN WEI

KUAN WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069410
    Abstract: A variable aperture module includes a blade assembly including movable blades, a positioning element including positioning structures and a driving part including a rotation element. The movable blades are disposed around an optical axis to form a light passable hole with adjustable size for different hole size states and each have an inner surface to define the contour of the light passable hole in each hole size state. The positioning structures correspond to the movable blades. The rotation element is rotatable with respect to the positioning element and is configured to rotate the movable blades to adjust a size of the light passable hole. There are matte structures disposed on each inner surface. Each matte structure is single structure extending towards the optical axis, such that at least part of the contour of the light passable hole has an undulating shape at least in several hole size states.
    Type: Application
    Filed: April 13, 2023
    Publication date: February 29, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Te-Sheng TSENG, Chen Wei FAN, Ming-Ta CHOU, Kuan-Ming CHEN
  • Publication number: 20240069618
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
  • Patent number: 11916128
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11911904
    Abstract: An apparatus for handling microelectronic devices comprises a pick arm having a pick surface configured for receiving a microelectronic device thereon, drives for moving the pick arm and reorienting the pick surface in the X, Y and Z planes and about a horizontal rotational axis and a vertical rotational axis, and a sensor device carried by the pick arm and configured to detect at least one of at least one magnitude of force and at least one location of force applied between the pick surface and a structure contacted by the pick surface or a structure and a microelectronic device carried on the pick surface.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kuan Wei Tseng, Brandon P. Wirz
  • Publication number: 20240064919
    Abstract: One aspect of the instant application describes a system that includes a plurality of stacked mezzanine boards communicatively coupled to a motherboard and a metal enclosure enclosing the motherboard and mezzanine boards. A respective mezzanine board can include a number of solder pads, and the metal enclosure can include a plurality of metal strips, a respective metal strip to make contact with a solder pad of a corresponding mezzanine board. The system can further include a logic module positioned on the respective mezzanine board to determine a location of the respective mezzanine board based on a contact pattern between the metal strips and solder pads of the respective mezzanine board.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Vincent Nguyen, Minh H. Nguyen, Kuan-Wei Chen
  • Publication number: 20240055323
    Abstract: A semiconductor device assembly including a through-silicon via (TSV) having an end region protruding from a back side of the substrate, the end region being surrounded by a conductive annulus disposed over the back side of the substrate; a dielectric layer disposed over the back side of the substrate, the dielectric layer having an upper surface flush with an upper surface of the end region of the TSV and flush with an upper surface of the conductive annulus; and a bond pad disposed over and electrically coupled to the end region of the TSV and the conductive annulus.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Ren Yuan Huang, Kuan Wei Tseng, Te Pao, Koji Torii
  • Patent number: 11892409
    Abstract: The present invention includes a shell, a light emitter, a beam splitter, a convergent lens, an optical filter, a collimation unit, a discrete light detection unit, and a processing unit. The shell includes a sample well to contain a sample. The light emitter generates a detection beam towards the beam splitter, the detection beam is reflected by the beam splitter before being converged by the convergent lens onto the sample, and a Raman scattered beam is scattered from the sample. The Raman scattered beam respectively passes through the convergent lens, the beam splitter, the optical filter, and the collimation unit, allowing the collimation unit to collimate the Raman scattered beam into a collimated beam. The discrete light detection unit generates multiple light intensity signals according to the collimated beam received, and the processing unit generates a detection result according to the light intensity signals to help detect toxins.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: February 6, 2024
    Assignee: Taiwan RedEye Biomedical Inc.
    Inventors: Tsung-Jui Lin, Shuo-Ting Yan, Kuan-Wei Su
  • Publication number: 20240021468
    Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.
    Type: Application
    Filed: August 8, 2023
    Publication date: January 18, 2024
    Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
  • Patent number: 11859038
    Abstract: A block copolymer of polyamide acid includes a first polyamide acid and a second polyamide acid alternately connected. The first polyamide acid is made by first dianhydride monomers and second diamine monomers. The second polyamide acid is made by second dianhydride monomers and first diamine monomers. Each first dianhydride monomer is or comprises a liquid crystal structure. Each second dianhydride monomer and each second diamine monomer respectively include a first flexible structure. Each first diamine monomer includes a liquid crystal structure. Each liquid crystal structure includes a cyclic group selected from a chemical structural formula of and intermediate groups selected from a chemical structural formula of Each flexible structure includes a group selected from a group consist of ether bond, ketone group, sulphone group, aliphatic hydrocarbon group, and any combination thereof.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: January 2, 2024
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Kuan-Wei Lee, Szu-Hsiang Su, Shou-Jui Hsiang, Pei-Jung Wu, Wei-Hsin Huang
  • Publication number: 20230420538
    Abstract: A semiconductor device includes a plurality of fin structures disposed over a substrate and a work function alloy layer disposed over each fin structure of the plurality of fin structures. The plurality of fin structures includes a first fin structure and a second fin structure. A content of a first element in a first portion of the work function alloy layer, which portion is disposed over the first fin structure, is different from a content of the first element in a second portion of the work function alloy layer, which portion is disposed over the second fin structure.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi PAN, Kuan-Wei Lin, Chun-Neng Lin, Yu-Shih Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230403948
    Abstract: Embodiments of the present disclosure provide a magnetic tunnel junction (MTJ) structure for storing a data. In one embodiment, the MJT structure includes a first ferromagnetic layer, a second ferromagnetic layer disposed above the first ferromagnetic layer, a first dielectric layer disposed between and in contact with the first ferromagnetic layer and the second ferromagnetic layer, a plurality of metal particles disposed in contact with the second ferromagnetic layer, wherein the metal particles are distributed in a discrete and non-continuous manner, and a second dielectric layer disposed over the plurality of metal particles.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Inventors: Hsuan-Yi PENG, Cherng-Yu WANG, Jen-Po LIN, Hsiao-Kuan WEI
  • Publication number: 20230395647
    Abstract: Embodiments of present disclosure provide a MIM capacitor including a straining layer on an electrode, and a high-k dielectric layer formed on the straining layer. The straining layer allows the high-k dielectric layer to be highly crystallized without requiring an extra annealing process. The high crystallization of the high-k dielectric layer results in increased the dielectric value (k-value), thus, improving capacitance density in the MIM capacitor. Some embodiments provide a MIM capacitor device including stacked MIM capacitors with symmetrically arranged high-k dielectric layers and straining layers.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Jen-Po LIN, Cherng-Yu WANG, Hsiao-Kuan WEI
  • Publication number: 20230384862
    Abstract: Broadly speaking, embodiments of the present techniques provide haptic button assemblies in which the haptic button has a low profile while still providing a satisfying tactile response or sensation to a user. Advantageously, the haptic button assemblies may have a profile that, for example, enables the assembly to be incorporated into the free space along an edge of a portable computing device. The haptic assemblies may, for example, be arranged to move the button perpendicularly with respect to the edge of the device.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: David Kuan Wei Ooi, Peter Van Wyk, Joshua Carr, Thomas James Powell, Marc-Sebastian Scholz, Andreas Flouris, Andrew Benjamin Simpson Brown, Stephen Matthew Bunting, Dominic George Webber, James Howarth
  • Patent number: 11830742
    Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
  • Patent number: 11823832
    Abstract: An alert system for a transformer includes a thermographic camera configured to capture thermal images of the transformer, a current sensor configured to generate a sensor signal indicating the current magnitude of a current outputted from the transformer, a storage configured to store a machine learning model, an alert device, and a processing unit configured to obtain image temperature values from the thermal images, obtain magnitude values from the sensor signal, obtain normal temperature values by using the machine learning model and the magnitude values, and instruct the alert device to deliver an alerting signal based on a result of comparison between the image temperature values and the normal temperature values.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: November 21, 2023
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Shun-Hung Tsai, Men-Shen Tsai, Kuan-Wei Ko
  • Patent number: 11807542
    Abstract: A method for preparing urea ammonium nitrate solution from waste nitric acid after stripping tin from circuit board includes: causing the waste nitric acid after stripping tin and the ammonia water to undergo neutralizing and precipitating reaction through acid-base neutralization, filtering, thereby obtaining tin-containing filter mud and a primary filtrate; adding iron powders into to the primary filtrate to initiate copper-iron replacement reaction, filtering, thereby obtaining iron-containing coarse copper powders and a secondary filtrate; adding hydrogen peroxide to the secondary filtrate, filtering, thereby obtaining an iron-containing sludge and a tertiary filtrate; adding a heavy metal capturing agent to the tertiary filtrate, filtering, thereby obtaining a heavy metal sludge and an ammonium nitrate solution; measuring a concentration of the ammonium nitrate solution, adding urea and liquid fertilizer corrosion inhibitor to obtain a urea/ammonium nitrate dilute solution, evaporating and concentrating
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 7, 2023
    Assignee: SHENZHEN ENVIRONMENTAL TECHNOLOGY GROUP CO. LTD.
    Inventors: Wei-Hong Wang, Jian-Gang Wu, Chao-Lin Mao, Chun-Hua Liao, Chang-Ming Chen, Kuan-Wei Huang, Xue-Qiang Huang
  • Publication number: 20230343640
    Abstract: A method for forming a conductive feature includes following operations. A first insulating layer is formed over a substrate. The first insulating layer is patterned to form a first recess in the first insulating layer. The first recess is filled with a conductive material. A plurality of second recesses are formed in the conductive material. Each of the second recesses overlaps the first recess. A portion of the conductive material is removed to form a first conductive feature. A ratio of a sum of opening areas of the second recesses to an opening area of the first recess is less than 1%.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Inventors: KUAN WEI SU, CHE-LI LIN, LING-SUNG WANG, LI-YI CHEN
  • Publication number: 20230335443
    Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Pan, Kuo-Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Yu-Te Su, Kuan-Wei Lin
  • Publication number: 20230335613
    Abstract: Provided is a semiconductor device including a first transistor of a first type comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second transistor of the first type comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.
    Type: Application
    Filed: June 19, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
  • Patent number: 11784056
    Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Huang, Yu-Yu Chen, Jyu-Horng Shieh