Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first channel member suspended over a substrate and a second channel member suspended over the first channel member and spaced apart from the first channel member along a first direction. The semiconductor structure also includes a gate structure wrapping around the first channel member and the second channel member and a dielectric structure encircled by the first channel member, the second channel member, the gate structure, and the source/drain structure. In addition, the dielectric structure includes a porous material or an air gap. The semiconductor structure also includes a first epitaxial layer attached to the first channel member, and the first epitaxial layer has a first extending portion protruding from a bottom surface of the first channel member along the first direction and extending into the dielectric structure.

Abstract: A hybrid permanent magnet motor rotor rotates around a central axis, and includes: a rotor core provided with a plurality of magnet installation slots; and a plurality of magnet parts embedded inside a plurality of magnet installation slots respectively, wherein the rotor is provided with a plurality of first magnetic pole parts and a plurality of second magnetic pole parts, the magnetic poles of the first magnetic pole part and the second magnetic pole part are arranged in opposite and alternately in the circumferential direction, and the magnetic placement of the first magnetic pole part is different from that of the second magnetic pole part, the amount of magnets used in the second magnetic pole part is greater than that used in the first magnetic pole part.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature coupled to the vertical stack of channel members and adjacent the gate structure; and a dielectric feature disposed between the source/drain feature and the substrate, in a cross-sectional view, the dielectric feature includes a V-shape sidewall surface.

Abstract: A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A certificate requesting method, a certificate issuing method, a certificate system and a computer-readable medium thereof are provided, in which subscriber identity identification information, a private key and a public key certificate bound to a first security chip are converted into a private key bound to a second security chip via an online identity authentication procedure, and the corresponding public key certificate is issued by a certificate authority server, so as to improve the usability, the convenience and the security thereof.

Abstract: The present disclosure relates to methods and systems for improving user experiences of an application. The methods and systems receive biological feedback of the user as the user interacts with an application and adapts the application's behavior in response to detecting a user's instantaneous reaction in response to interactions with the application. The methods and systems use a machine learning model to compare the user's current state based on the biological feedback received to known states to determine the user's instantaneous reaction to interactions with the application. The methods and systems provide feedback with a user experience classification of the user's interactions with the application.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: A Bluetooth transmitter, a Bluetooth receiver, and a receiver are provided. The Bluetooth transmitter includes modulation modules, up-conversion modules, and an RF transmitting circuit. The modulation modules modulate transmission bitstreams to generate multiple pairs of modulated signals. The up-conversion modules up-convert the pairs of modulated signals to multiple pairs of up-converted signals. The RF transmitting circuit transmits an output signal based on the pairs of up-converted signals. The Bluetooth receiver includes an RF receiving circuit, down-conversion modules, and de-modulators. The RF receiving circuit transforms an input signal into a pair of analog filtered signals. The down-conversion modules generate pairs of down-converted signals based on the pair of analog filtered signals. The de-modulators generate received bitstreams by demodulating the pairs of down-converted signals.

Abstract: A Bluetooth transmitter, a Bluetooth device, and a transmitter are provided. After being received by the transmitter, a transmission bitstream is modulated to generate a first-path modulated signal and a second-path modulated signal, which are up-converted to a first first-path up-converted signal, a second first-path up-converted signal, a first second-path up-converted signal, and a second second-path up-converted signal. The first first-path and the second first-path up-converted signals are corresponding to a first broadcast channel, and the first second-path and the second second-path up-converted signals correspond to a second broadcast channel. A first-path baseband signal is generated based on the first first-path and the second first-path up-converted signals, and a second-path baseband signal is generated based on the first second-path and the second second-path up-converted signals. A broadcast signal is generated based on the first-path and the second-path baseband signals.

Abstract: A method for starting a motor having a stator and a rotor is provided. The method includes starting a motor with field coils of the stator being in Y connection, switching the connection of the field coils to ? connection when the speed of the rotor does not fall within a predetermined range from a rated speed within a predetermined time (t2), and switching the connection of the field coils to the Y connection when the speed of the rotor falls within the predetermined range from the rated speed.

Abstract: Disclosed is a plasma treatment apparatus, a lower electrode assembly and a forming method thereof, wherein the lower electrode assembly includes: a base for carrying a substrate to be treated; a focus ring encircling a periphery of the base; a coupling loop disposed below the focus ring; a conductive layer disposed in the coupling loop; and a wire for electrically connecting the conductive layer and the base so that the base and the conducting layer are equipotential. The lower electrode assembly is less prone to cause arc discharge.

Abstract: A plasma reactor includes: a process chamber, at the inner bottom of the process chamber being provided a base, the base being connected to a RF power source via a RF match network, wherein a to-be-processed wafer is held above the base, an upper electrode assembly is provided at the inner top of the process chamber, and a plasma processing space is arranged between the base and the upper electrode assembly; a first conductive ground ring surrounding the outer periphery of the base; a second conductive ground ring connected between the outer sidewall of the first conductive ground ring and the inner sidewall of the process chamber, a plurality of gas channels being provided on the second conductive ground ring such that gas in the plasma processing space can be exhausted through the plurality of gas channels; an insulating ring provided between the base and the first conductive ground ring, wherein dielectric constant of the insulating ring is less than 3.5.

Abstract: A gas barrier laminate includes an organic layer and an inorganic layered unit. The organic layer includes a product obtained by subjecting a silane compound having an alkoxy group to hydrolysis and condensation. The inorganic layered unit is disposed on the organic layer, and includes an aluminum oxide layer, a hafnium oxide layer, and a silicon aluminum oxide layer that are laminated to one another.