Abstract: A method for forming a semiconductor device structure is disclosed. The method includes forming one or more first conductive features in a first dielectric layer, forming a metal layer on each of the one or more first conductive features, forming a first etch stop layer over the metal layer, forming a second etch stop layer on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer. The method also includes forming a second dielectric layer on the second etch stop layer, and forming a second conductive feature in the second dielectric layer through the second etch stop layer, the first etch stop layer, and the metal layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: An electronic device including a first substrate, a first semiconductor, a second semiconductor and a shielding element is disclosed. The first substrate has a peripheral region. The first semiconductor is disposed on the first substrate and in the peripheral region. The second semiconductor is disposed on the first substrate and in the peripheral region, and the first semiconductor is electrically connected to the second semiconductor. The shielding element is disposed on the first substrate and in the peripheral region, and the shielding element overlaps the first semiconductor and the second semiconductor.

Abstract: A synchronous reluctance motor includes magnetic barriers in each magnetic barrier group of a rotor core, each having a shape which protrudes toward a radial inner side and is symmetrical about a q-axis. A portion closer to a circumferential side than the q-axis includes a first portion extending perpendicular to the q-axis and a second portion extending farther toward the circumferential side from a circumferential side of the first portion and radially outward, and the first portions of the magnetic barriers in each magnetic barrier group have the same radial dimension. The first portions of the magnetic barriers other than the radial outermost magnetic barrier have the same circumferential dimension, which is the same as or twice a circumferential dimension of the first portion of the radial outermost magnetic barrier.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a conductive terminal. The first die includes a first connector, and the second die includes a second connector. The first encapsulant includes: a first portion, on the second die; a second portion, sandwiched between a first sidewall of the first die and a first sidewall of the second die; and a third portion, covering a second sidewall of the second die. The second encapsulant, laterally encapsulating the first die, the second die and the first encapsulant. The conductive terminal, electrically connected to the first die and the second die through a redistribution layer (RDL) structure. The third portion of first encapsulant is sandwiched between the second sidewall of the second die and the second encapsulant.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.

Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.

Abstract: A method for manufacturing a semiconductor device includes preparing an electrically conductive structure including a plurality of electrically conductive features, conformally forming a thermally conductive dielectric capping layer on the electrically conductive structure, conformally forming a dielectric coating layer on the thermally conductive dielectric capping layer, filling a sacrificial material into recesses among the electrically conductive features, recessing the sacrificial material to form sacrificial features in the recesses, forming a sustaining layer over the dielectric coating layer to cover the sacrificial features, and removing the sacrificial features to form air gaps covered by the sustaining layer. The thermally conductive dielectric capping layer has a thermal conductivity higher than that of the dielectric coating layer.

Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature, a first liner having a first top surface disposed on the first conductive feature, a second conductive feature disposed adjacent the first conductive feature, and a second liner disposed on at least a portion of the second conductive feature. The second liner has a second top surface, and the first liner and the second liner each comprises a two-dimensional material. The structure further includes a first dielectric material disposed between the first and second conductive features and a dielectric layer disposed on the first dielectric material. The dielectric layer has a third top surface, and the first, second, and third top surfaces are substantially co-planar.

Abstract: A package module includes an interposer, a plurality of semiconductor dies on the interposer and including a semiconductor die upper surface, an upper molding material layer on the plurality of semiconductor dies and including a recessed upper surface that is recessed from the semiconductor die upper surface, and a backside metal layer on the recessed upper surface of the upper molding material layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.

Abstract: One aspect of a rotor of the present disclosure is a rotor that includes a rotor core extending along the axial direction and a plurality of auxiliary magnets disposed in the rotor core. The rotor core includes a slit group including a plurality of first slits aligned in a radial direction, and a second slit disposed radially inside the slit group when viewed from the axial direction. The first slit extends along the circumferential direction in a shape protruding radially inward when viewed from the axial direction. The second slit includes a magnet housing portion extending along the radial direction, and a pair of outer flux barrier portions. The auxiliary magnet is disposed in the magnet housing portion with the circumferential direction as the magnetization direction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure, a second fin structure, and a third fin structure over the substrate. Tops of the second fin structure and the third fin structure are at different height levels. The semiconductor device structure also includes a first epitaxial structure extending across sidewalls of the first fin structure and the second fin structure and a second epitaxial structure on the third fin structure. The first epitaxial structure is closer to the substrate than the second epitaxial structure.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.