Patents by Inventor Kuan Yang
Kuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20100065032Abstract: A manually and electrically actuating toy gun structure includes a gun shell, a trigger, a gun machine core tube, and a piston. The control structure includes a first interlocking rod, a first push member, a second interlocking rod, a transmission set, a triggering device, a gun shell, and a push-and-propping-up block. One end of the first interlocking rod has a connecting pin interlocking with the first push member. The other end of the first interlocking rod has a connecting hole connecting to the trigger and being driven to slide along the x-direction. The hole of the first push member is connected to a connecting end of the first interlocking rod and is contacted with the push-and-pluck rod of the switch. The power supply of the electric motor is switched on when the first push member is driven by the first interlocking rod to push the push-and-pluck rod.Type: ApplicationFiled: November 6, 2008Publication date: March 18, 2010Inventor: Chung-Kuan Yang
-
Publication number: 20100065033Abstract: A duplex control structure of toy gun includes a main body (3), a control portion (1), a transmission portion (2), and a motor (4). The main body (3) further consists of a left and right main bodies (3a), (3b), a barrel (31), two motor's positioning plates (32a) and (32b), a multiplicity of supporting shaft rods (33), (34), a left and right handle portions (35a), (35b), check plates (36a), (36b), and two sliding ways (37a), (37b). The control portion (1) further consists of a trigger (11), a control rod (12), a propping up plate (13), a brake (14), a slider rod (15), a positioning plate (25), a pull knob (17), and a power switch (18). The transmission portion (2) consists of a gun machine socket (21), a piston (22), springs (23), (24), a positioning plate (25), a check piece (26), a clip piece (27), a small transmission gear (28), and a large transmission gear (29). The motor (4) is connected to a DC power supply.Type: ApplicationFiled: December 3, 2008Publication date: March 18, 2010Inventor: Chung-Kuan Yang
-
Publication number: 20090302043Abstract: The present invention provides a wash-free dinnerware, which is characterized in that, the surface of the wash-free dinnerware is provided with an insulating layer made of food-grade, high-temperature thermoplastic or thermosetting plastic materials; the insulating layer is formed onto the surface of wash-free dinnerware by means of thermal shrinkage, or immersion or blowing. So, the insulating layer could prevent direct contact of wash-free dinnerware with food.Type: ApplicationFiled: June 10, 2008Publication date: December 10, 2009Applicants: LIANZHUN TECHNOLOGY CORPORATION, Mr. Yao Ming Yang, Mr. Kuan Yang ChenInventors: Yao Ming Yang, Kuan Yang Chen, Pi Chen Chen
-
Publication number: 20090256743Abstract: The present invention discloses a mobile positioning and tracking system that includes a master device and a slave device. Within a tracking range of the master device, a satellite is used for receiving a signal from the slave device, and then transmitting the signal to the master device to display an initial location of the slave device. Meanwhile, the master device compares the location of the master device with a relative direction, distance, height or angle of the location of the satellite signal received by the master device, such that the master device can search according to the relative location. If the slave device is situated within the tracking range of the master device, Zigbee is used for receiving a signal from the slave device to estimate the location of a target outside the tracking range, and accurately measure the relative location of the target within the tracking range.Type: ApplicationFiled: April 14, 2008Publication date: October 15, 2009Applicants: LIANZHUN TECHNOLOGY CORPORATIONInventors: Kuan Yang Chen, Yao Ming Yang
-
Patent number: 7595234Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: GrantFiled: September 15, 2006Date of Patent: September 29, 2009Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
-
Publication number: 20090050515Abstract: A sterilized disposable cap for a dinner set that can be firmly secured to an outer surface at the front end of a chopstick to avoid direct contact of the food includes a tube having an opening end and a closed end; a straight section in same diameter as that of the tube extends from the opening end towards the closed section; a tapered section is formed to the straight section upon approaching the closed end; one or a plurality of flute is axially disposed on and in parallel with a surface of the tube; the flute extends from the opening end of the tube until approaching the closed end.Type: ApplicationFiled: August 22, 2007Publication date: February 26, 2009Inventors: Yao-Ming Yang, Kuan-Yang Chen
-
Patent number: 7462542Abstract: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.Type: GrantFiled: November 7, 2007Date of Patent: December 9, 2008Assignee: United Microelectronics Corp.Inventors: Alex Liu, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
-
Patent number: 7367507Abstract: An optical scanning module includes a housing, a light source and a first heat-dissipating sheet. The light source is disposed inside the housing for emitting a source light to be projected onto the object. The light source includes an electrode wrapped by an electric-insulating and heat-conducting rubber. The first heat-dissipating sheet is arranged on a surface of the housing and in contact with the electric-insulating and heat-conducting rubber.Type: GrantFiled: June 5, 2006Date of Patent: May 6, 2008Assignee: Primax Electronics Ltd.Inventors: Hsi-Yu Chen, Kuan-Yang Chen
-
Publication number: 20080057655Abstract: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.Type: ApplicationFiled: November 7, 2007Publication date: March 6, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Alex Liu, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
-
Patent number: 7326622Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.Type: GrantFiled: November 8, 2005Date of Patent: February 5, 2008Assignee: United Microelectronics Corp.Inventors: Yi-Cheng Liu, Jiunn-Ren Hwang, Wei-Tsun Shiau, Cheng-Tung Huang, Kuan-Yang Liao
-
Patent number: 7319063Abstract: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.Type: GrantFiled: February 2, 2005Date of Patent: January 15, 2008Assignee: United Microelectronics Corp.Inventors: Wen-Shiang Liao, Wei-Tsun Shiau, Kuan-Yang Liao
-
Patent number: 7297025Abstract: An electrical connector includes an insulative housing, a plurality of terminals, a holding member and a shielding covering having a latch element, wherein the holding member including a plurality of resilient plates, a coupling portion for coupling the resilient plates, and a pair of extending portions. In assembly, the holding member is inserted into the insulative housing in a direction of the rear face of the insulative housing and therefore the extending portion adheres to the rear face, then the shielding covers the insulative housing in a direction of the front face of the insulative housing and therefore the latch element is inserted through the slot and interferentially contacting the extending portion of the holding member.Type: GrantFiled: May 17, 2006Date of Patent: November 20, 2007Assignee: P-Two Industries Inc.Inventor: Kuan-Yang Wei
-
Publication number: 20070194120Abstract: An optical scanning module includes a housing, a light source and a first heat-dissipating sheet. The light source is disposed inside the housing for emitting a source light to be projected onto the object. The light source includes an electrode wrapped by an electric-insulating and heat-conducting rubber. The first heat-dissipating sheet is arranged on a surface of the housing and in contact with the electric-insulating and heat-conducting rubber.Type: ApplicationFiled: June 5, 2006Publication date: August 23, 2007Applicant: Primax Electronics Ltd.Inventors: Hsi-Yu Chen, Kuan-Yang Chen
-
Publication number: 20070195440Abstract: A scanning module of an image scanner for scanning a document is provided. The scanning module of the image scanner includes a base, a reflective mirror stand, a shaft, a reflective mirror member and a gear set. The reflective mirror stand is mounted on the base. The shaft is rotatably mounted on the reflective mirror stand. The reflective mirror member is fixed on the shaft and rotated with the shaft. The gear set is pivotally coupled to the shaft for rotating and driving the shaft to adjust the reflective angle of the reflective mirror member, which is fixed on the shaft.Type: ApplicationFiled: June 5, 2006Publication date: August 23, 2007Applicant: Primax Electronics Ltd.Inventors: Hsi-Yu Chen, Kuan-Yang Chen
-
Patent number: 7256914Abstract: An optical scanner for scanning a document includes a housing, a glass platform, an optical scanning module and a heat dissipating member. The glass platform is disposed on the housing for placing thereon the document to be scanned. The optical scanning module is disposed inside the housing for scanning the document. The heat dissipating member is disposed inside the housing and in contact with a first lateral edge of the glass platform for conducting the heat generated from the optical scanning module to the glass platform such that the heat is then radiated from the glass platform to the outside of the housing.Type: GrantFiled: June 5, 2006Date of Patent: August 14, 2007Assignee: Primax Electronics Ltd.Inventors: Hsi-Yu Chen, Kuan-Yang Chen
-
Publication number: 20070126032Abstract: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.Type: ApplicationFiled: February 12, 2007Publication date: June 7, 2007Inventors: WEN-SHIANG LIAO, Wei-Tsun Shiau, Kuan-Yang Liao
-
Patent number: 7220647Abstract: A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.Type: GrantFiled: February 2, 2005Date of Patent: May 22, 2007Assignee: United Microelectronics Corp.Inventors: Chih-Ning Wu, Charlie C J Lee, Kuan-Yang Liao
-
Patent number: 7214988Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: GrantFiled: September 20, 2005Date of Patent: May 8, 2007Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
-
Patent number: 7196019Abstract: A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.Type: GrantFiled: December 21, 2004Date of Patent: March 27, 2007Assignee: United Microelectronics Corp.Inventors: Chih-Ning Wu, Charlie C J Lee, Kuan-Yang Liao
-
Publication number: 20070063290Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao