Abstract: A method of fabricating a metal gate includes forming a gate insulating layer on a provided substrate, forming a PVD titanium nitride layer on the gate insulating layer, forming a CVD titanium nitride layer on the PVD titanium nitride layer, and forming a CVD tungsten layer on the CVD titanium nitride layer. The CVD tungsten layer, the CVD titanium nitride layer, and the PVD titanium nitride layer are later patterned to form the metal gate.

Abstract: A method for manufacturing the capacitor of a dynamic random access memory cell. The method includes the steps of first providing a substrate having field effect transistors thereon, and then forming a dielectric layer over the substrate. Next, a contact opening that exposes the source/drain region is formed in the dielectric layer, and then conductive material is deposited over the substrate, filling the contact opening to form a conductive layer. Thereafter, the conductive layer is patterned, and then a portion of the exposed dielectric layer is removed to form trenches that surround the conductive layer. In the subsequent step, conductive spacers are formed on the sidewalls of the trenches and the conductive layer. The conductive spacers and the conductive layer form the lower electrode structure of a capacitor.

Abstract: A fabrication method for a sharp tip emitter first includes a trench formed on a semiconductor substrate. Next, an isolating layer is deposited over the substrate by high-density plasma chemical vapor deposition (HDP CVD). A V-shaped groove is naturally formed on the isolating layer around the trench. Next, a silicon layer is formed over the isolating layer and an ion implantation is performed into the silicon layer over the V-shaped groove. Next, a semiconductor layer is formed over the substrate. Next, a high temperature thermal process is performed to drive the implanted ions into the semiconductor layer. Next, the isolating layer is removed so that the silicon layer is separated from the substrate. Then, the tip emitter is formed.

Abstract: A method of forming a contact diffusion barrier in a thin geometry integrated circuit device involves implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired. The low resistivity and implanted materials are selected to intereact with each other and form a contact diffusion barrier. Both materials may include transition metals, in which case the diffusion barrier is a composite transition metal. Alternately, the low resistivity material may include a transition metal, while implantation is performed with nitrogen. The implantation is performed by plasma etching, preferably with active cooling, which can be combined in a continuous step with the etching of the contact opening. The resulting contact diffusion barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.

Abstract: A modification of the self-aligned double poly fabrication process for bipolar transistors employs a thin sacrificial dielectric film to protect the wafer surface during the etching of an emitter opening through an overlying polysilicon contact layer. The sacrificial layer, which is preferably silicon dioxide for a silicon wafer, is thick enough to serve as an etch stop but thin enough to permit dopant from the polysilicon contact to be driven-in through the film to form an extrinsic base region. The dielectric film is left in place under the base contact polysilicon, but removed from the emitter area. It is preferably about 10-20 Angstroms thick when implemented as a silicon dioxide film. With this material system, the extrinsic base drive-in is preferably performed either by a rapid isothermal anneal at about 1,000.degree. C. for about 30-40 seconds, or in a furnace at about 975.degree. C. for about 10 minutes.

Abstract: A complementary bipolar CMOS fabrication method uses a common deposition for both the CMOS gate contacts, and as a sacrificial layer for patterning bipolar devices. The deposition is removed from the bipolar devices and, after implanting base and emitter regions, is replaced with a separate emitter contact. Prior to its removal the sacrificial layer is coated with an oxidation resistant layer that imparts a desirable rounded shape to the edge of a thermal oxide layer that is grown around the bipolar emitter area. Common mask and implant steps are also used to fabricate lightly doped CMOS drains together with bipolar base-link regions, and CMOS source/drain regions together with bipolar external base regions. The fabrication technique also facilitates the fabrication of capacitors with no additional steps required, and includes an improved NiCr resistor contact method.

Abstract: A method of forming a contact diffusion barrier in a thin geometry integrated circuit device involves implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired. The low resistivity and implanted materials are selected to intereact with each other and form a contact diffusion barrier. Both materials may include transition metals, in which case the diffusion barrier is a composite transition metal. Alternately, the low resistivity material may include a transition metal, while implantation is performed with nitrogen. The implantation is performed by plasma etching, preferably with active cooling, which can be combined in a continuous step with the etching of the contact opening. The resulting contact diffusion barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.

Abstract: A process for forming a diffusion barrier on exposed silicon and polysilicon contacts of an integrated circuit including the step of chemically vapor depositing a layer of tungsten in a self-aligned manner on the exposed contact areas. The layer of tungsten is plasma nitridated to form a tungsten nitride layer and to partially form a tungsten silicide layer adjacent the contact areas. The formation of the tungsten silicide layer is completed by thermal annealing.