Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, wherein each of the blocks has a plurality of pages. The controller receives a plurality of write commands in a sequence, assigns a plurality of write sequence numbers to the write commands according to the sequence in which the write commands are received, and writes a plurality of data sectors and the write sequence numbers of the write commands into the pages of a first current block and a second current block of the blocks according to the write commands.

Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of planes, and each plane includes a plurality of blocks. A portion of blocks in each of the planes constitutes a super block, so that the flash memory includes a plurality of super blocks. The controller is coupled to the flash memory. When a first block of at least one first super block of the super blocks is damaged, and a second block of a second super block in the position corresponding to the damaged block is normal, the controller merges the second block of the second super block with the first super block to replace the first block. The random-access memory stores a compression table to record position information about the first block in the first super block and the number information of the second block.

Abstract: The present invention provides a method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of first temporary blocks and a plurality of second temporary blocks, each of the first and second temporary blocks and the data blocks includes a plurality of pages, and the method includes: writing data into one of the second temporary blocks; and when an access of the flash memory module meets a specific condition, moving the data stored in the second temporary block to one of the first temporary blocks, and storing information of a first blank page of the second temporary block to the first temporary block.

Abstract: The present invention provides a data storage device including a flash memory and a random access memory. The flash memory has a data mapping table arranged to record a plurality of mapping relationships between the logical addresses and the physical addresses of a plurality of pages of the flash memory. The data mapping table is divided into a plurality of data mapping sets. The random access memory has a cache area, a sequential-order table, a reverse-order table and a cache-area mapping table. The cache area stores part of the data mapping sets. The cache-area mapping table records the set indexes of the data mapping sets of the cache area. The sequential-order table records the order that the data mapping sets are read from the cache area. The reverse-order table records the opposite order that the data mapping sets are read from the cache area.

Abstract: The invention introduces a method for GC (garbage collection) POR (Power Off Recovery), performed by a processing unit, including at least the following steps: after a reboot subsequent to a power-off event, reading a GC recovery flag from a storage unit and determining whether the GC recovery flag indicates that a flash memory needs a POR; and, when the GC recovery flag indicates that the flash memory needs a POR, programming dummy data into a predefined number of empty pages next to the last programmed page of a destination block of the storage unit and performing an unfinished GC data-access operation.

Abstract: The invention introduces a method for regular and garbage-collection data access, performed by a processing unit, including at least the following steps: configuring a data buffer as a first type when performing a data access operation of a regular data access mode; and configuring the data buffer as a second type when performing a data access operation of a garbage-collection data access mode.

Abstract: The invention introduces a method for garbage collection, performed by a processing unit, including at least the following steps: executing instructions of a GC (garbage collection) process to direct a first access interface to read data from a storage unit, collect good data from the read data and direct the first access interface to program the good data into a spare block of the storage unit. During the GC process, each time that a timer has counted to a time period, the processing unit directs a second access interface to clock a portion of data requested by a host device out to the host device and resets the timer.

Abstract: The present invention provides a data storage device including a random access memory and a controller. The random access memory has a cache area. The controller loads a part of data mapping sets of the data mapping table on a plurality of sectors of the cache area, wherein any of the data mapping sets that has been read less than a predetermined number of times is defined as an infrequent data mapping set, and any of the data mapping sets that has been read more than the predetermined number of times is defined as a frequent data mapping set.

Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks. Each block includes a plurality of pages. when the data storage device is resumed from a power-off event, the controller selects a first block which was written last before the power-off event among the plurality of blocks and writes data of a plurality of first pages of the first block into a plurality of second pages of the first block.

Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks. Each block includes a plurality of pages. when the data storage device is resumed from a power-off event, the controller selects a first block which was written last before the power-off event among the plurality of blocks and writes data of a plurality of first pages of the first block into a plurality of second pages of the first block.

Abstract: The present invention provides a data storage device including a random access memory and a controller. The random access memory has a cache area. The controller loads a part of data mapping sets of the data mapping table on a plurality of sectors of the cache area, wherein any of the data mapping sets that has been read less than a predetermined number of times is defined as an infrequent data mapping set, and any of the data mapping sets that has been read more than the predetermined number of times is defined as a frequent data mapping set.

Abstract: For single-level cell flash memories and multi-level cell flash memories, different operations can be performed according to their stability when an abnormal status is terminated. Specifically, for the multi-level cell flash memories, when the abnormal status is terminated, a now physical block is used to proceed with write operation, and the previous physical block(s) would not be written any more. On the contrary, for the single-level cell flash memories, when the abnormal status is terminated, the controller needs to perform corresponding operations on the last physical page of the previous physical block(s).

Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks. Each block includes a plurality of pages. when the data storage device is resumed from a power-off event, the controller selects a first block which was written last before the power-off event among the plurality of blocks and writes data of a plurality of first pages of the first block into a plurality of second pages of the first block.

Abstract: For single-level cell flash memories and multi-level cell flash memories, different operations can be performed according to their stability when an abnormal status is terminated. Specifically, for the multi-level cell flash memories, when the abnormal status is terminated, a now physical block is used to proceed with write operation, and the previous physical block(s) would not be written any more. On the contrary, for the single-level cell flash memories, when the abnormal status is terminated, the controller needs to perform corresponding operations on the last physical page of the previous physical block(s).

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of blocks. Each of the blocks has a plurality of pages. The flash memory stores data of a plurality of logical addresses. The controller reads a first current block and a second current block from the flash memory in sequence to build a first current block table and a second current block table and builds a bit table according to the logical addresses of the pages of the second current block when the data storage device is resumed from a power-off state, wherein the controller further organizes the first current block table and the second current block table according to the bit table.

Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks. Each block includes a plurality of pages. when the data storage device is resumed from a power-off event, the controller selects a first block which was written last before the power-off event among the plurality of blocks and writes data of a plurality of first pages of the first block into a plurality of second pages of the first block.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, wherein each of the blocks has a plurality of pages. The controller receives a plurality of write commands in a sequence, assigns a plurality of write sequence numbers to the write commands according to the sequence in which the write commands are received, and writes a plurality of data sectors and the write sequence numbers of the write commands into the pages of a first current block and a second current block of the blocks according to the write commands.

Abstract: The present invention provides a data storage device including a flash memory and a random access memory. The flash memory has a data mapping table arranged to record a plurality of mapping relationships between the logical addresses and the physical addresses of a plurality of pages of the flash memory. The data mapping table is divided into a plurality of data mapping sets. The random access memory has a cache area, a sequential-order table, a reverse-order table and a cache-area mapping table. The cache area stores part of the data mapping sets. The cache-area mapping table records the set indexes of the data mapping sets of the cache area. The sequential-order table records the order that the data mapping sets are read from the cache area. The reverse-order table records the opposite order that the data mapping sets are read from the cache area.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a non-volatile memory, a connection interface, and a controller. The non-volatile memory is divided into a plurality of physical blocks. Each physical block is divided into a plurality of physical pages. The connection interface is connected to a host. The controller is connected to the connection interface. When the controller performs a block-reconfiguration operation, the controller re-adjusts a position in the physical blocks where data is disposed to obtain a usable physical block. Movement of one portion of the data related to the block-reconfiguration operation is performed when the controller operates an initial operation. Movement of another portion of the data related to the block-reconfiguration operation is performed when the controller processes a read command from the host.

Abstract: A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels.