Patents by Inventor Kuan-Yu Wang

Kuan-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240290659
    Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.
    Type: Application
    Filed: April 29, 2024
    Publication date: August 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi LEE, Kuan-Yu WANG, Cheng-Lung HUNG, Chi-On CHUI
  • Patent number: 12002714
    Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Kuan-Yu Wang, Cheng-Lung Hung, Chi-On Chui
  • Publication number: 20220384267
    Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi LEE, Kuan-Yu WANG, Cheng-Lung HUNG, Chi-On CHUI
  • Patent number: 11450569
    Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Kuan-Yu Wang, Cheng-Lung Hung, Chi-On Chui
  • Publication number: 20220093468
    Abstract: A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi LEE, Kuan-Yu WANG, Cheng-Lung HUNG, Chi-On CHUI
  • Patent number: 10927000
    Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: February 23, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
  • Patent number: 10804664
    Abstract: The invention is related to a crimp tool having an adjustable cam for accomplishing precision machining of a connector with a cable. The adjustable cam is provided at one of the handles of the crimp tool and is configured to prevent a moving handle of the crimp tool from moving beyond the adjustable cam so as to allow a user to adjust the pivot range of the moving handle, which controls the extent of the movement of a machining block in a machining portion of the crimp tool.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 13, 2020
    Inventors: Robert W. Sullivan, Kuan Yu Wang, Wen-Lung Hung
  • Patent number: 10475640
    Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
  • Patent number: 10457546
    Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: October 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
  • Patent number: 10427935
    Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
  • Publication number: 20190027358
    Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 24, 2019
    Inventors: YAN-DA CHEN, WENG YI CHEN, CHANG-SHENG HSU, KUAN-YU WANG, YUAN SHENG LIN
  • Publication number: 20190016591
    Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 17, 2019
    Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
  • Patent number: 10112825
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
  • Patent number: 10115582
    Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 30, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yan-Da Chen, Weng Yi Chen, Chang-Sheng Hsu, Kuan-Yu Wang, Yuan Sheng Lin
  • Publication number: 20180208460
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
    Type: Application
    Filed: March 3, 2017
    Publication date: July 26, 2018
    Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
  • Publication number: 20180205194
    Abstract: The invention is related to a crimp tool having an adjustable cam for accomplishing precision machining of a connector with a cable. The adjustable cam is provided at one of the handles of the crimp tool and is configured to prevent a moving handle of the crimp tool from moving beyond the adjustable cam so as to allow a user to adjust the pivot range of the moving handle, which controls the extent of the movement of a machining block in a machining portion of the crimp tool.
    Type: Application
    Filed: December 5, 2017
    Publication date: July 19, 2018
    Inventors: ROBERT W. SULLIVAN, KUAN YU WANG, WEN-LUNG HUNG
  • Publication number: 20180201498
    Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.
    Type: Application
    Filed: March 14, 2018
    Publication date: July 19, 2018
    Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
  • Patent number: 9950920
    Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
  • Publication number: 20170210615
    Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
  • Patent number: 9668064
    Abstract: A microelectromechanical system microphone includes a semiconductor-on-insulator structure, a plurality of resistors, a plurality of first openings, and a vent hole. The semiconductor-on-insulator structure includes a substrate, an insulating layer and a semiconductor layer. The resistors are formed in the semiconductor layer, the first openings are formed in the semiconductor layer, and the vent hole is formed in the insulating layer and the substrate. The resistors are connected to each other to form a resistor pattern, and the first openings are all formed within the resistor pattern.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: May 30, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Sheng Hsu, Yuan-Sheng Lin, Wei-Hua Fang, Kuan-Yu Wang, Yan-Da Chen