Patents by Inventor Kuan-Yu Wang

Kuan-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9624092
    Abstract: A semiconductor structure having micro-electro-mechanical system (MEMS) devices is provided. One of the MEMS devices includes a substrate having a first region and a second region; a membrane structure formed in the first region and positioned correspondingly to a cavity of the substrate; a logic device formed in the second region, and electrically connected to the membrane structure; an interconnection structure formed in the second region, and the interconnection structure formed on the substrate and covering the logic device; and an etching stop layer formed in the second region, and the etching stop layer formed on the interconnection structure and including a nitride layer and a carbon-containing layer formed on the nitride layer. Also, a variation in resonant frequencies of the MEMS devices on the entire wafer is less than 10%.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hua Fang, Kuan-Yu Wang, Her-Yi Tang, Xuan-Rui Chen
  • Publication number: 20170036905
    Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 9, 2017
    Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
  • Publication number: 20160355398
    Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 8, 2016
    Inventors: YAN-DA CHEN, WENG YI CHEN, CHANG-SHENG HSU, KUAN-YU WANG, YUAN SHENG LIN
  • Patent number: 9499399
    Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
  • Publication number: 20160212551
    Abstract: A microelectromechanical system microphone includes a semiconductor-on-insulator structure, a plurality of resistors, a plurality of first openings, and a vent hole. The semiconductor-on-insulator structure includes a substrate, an insulating layer and a semiconductor layer. The resistors are formed in the semiconductor layer, the first openings are formed in the semiconductor layer, and the vent hole is formed in the insulating layer and the substrate. The resistors are connected to each other to form a resistor pattern, and the first openings are all formed within the resistor pattern.
    Type: Application
    Filed: February 24, 2015
    Publication date: July 21, 2016
    Inventors: Chang-Sheng Hsu, Yuan-Sheng Lin, Wei-Hua Fang, Kuan-Yu Wang, Yan-Da Chen
  • Patent number: 8936960
    Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Kuan-Yu Wang, Hui-Min Wu, Kun-Che Hsieh
  • Publication number: 20150011035
    Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 8, 2015
    Inventors: Kuan-Yu Wang, Hui-Min Wu, Kun-Che Hsieh
  • Publication number: 20140367805
    Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
  • Patent number: 8525354
    Abstract: A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: September 3, 2013
    Assignee: United Microelectronics Corporation
    Inventors: Hui-Min Wu, Ming-I Wang, Kuan-Yu Wang, Kun-Che Hsieh, Chien-Hsin Huang
  • Publication number: 20130093104
    Abstract: A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hui-Min WU, Ming-I Wang, Kuan-Yu Wang, Kun-Che Hsieh, Chien-Hsin Huang
  • Patent number: 8310065
    Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: November 13, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Hui-Min Wu, Bang-Chiang Lan, Chien-Hsin Huang, Kuan-Yu Wang, Chao-An Su, Tzung-I Su
  • Publication number: 20120175778
    Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Inventors: Hui-Min Wu, Bang-Chiang Lan, Chien-Hsin Huang, Kuan-Yu Wang, Chao-An Su, Tzung-I Su