Patents by Inventor Kuang C. Liu

Kuang C. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11737227
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gregorio R. Murtagian, Kuang C. Liu, Kemal Aygun
  • Publication number: 20220183177
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Inventors: Zhichao ZHANG, Gregorio R. MURTAGIAN, Kuang C. LIU, Kemal AYGUN
  • Patent number: 11291133
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gregorio R. Murtagian, Kuang C Liu, Kemal Aygun
  • Patent number: 10680367
    Abstract: Embodiments of the disclosure are directed to a linear edge connector assembly for connecting to a substrate diving board of a mother board. The linear edge connector assembly can include an electrical interface to electrically connect the contacts on the diving board to one or more conducts of a cable bundle. The linear edge connector assembly can also include a retaining force mechanism. The retaining force mechanism can include a torsional spring, a spring loaded hooking mechanism, or a spring loaded cam and lever. In some embodiments, the linear edge connector can include a notch to receive a latch connected to a bolster plate on the mother board.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Anthony P. Valpiani, Jonathon Robert Carstens
  • Publication number: 20190307009
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Zhichao ZHANG, Gregorio R. MURTAGIAN, Kuang C. LIU, Kemal AYGUN
  • Publication number: 20190307010
    Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket, a method of forming the TL-LGA socket, and a semiconductor package assembly. The TL-LGA socket includes interconnects having a vertical portion and a horizontal portion. The TL-LGA socket has a housing body, where the vertical portions are disposed in the housing body, and the interconnects are disposed in the housing body in a cascaded configuration. The interconnect may have the horizontal portion coupled to the vertical portion and a pad on a conductive base layer of a package. The conductive base layer may include pads and corresponding pad openings surrounding the pads. The TL-LGA socket may have the horizontal portion disposed between and parallel to the base layer and a top conductive layer of the housing body. The TL-LGA socket may have the base layer and/or the conductive layer coupled to a ground reference.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Zhichao ZHANG, Kuang C. LIU, Kemal AYGUN, Baris BICEN
  • Publication number: 20190182955
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate. The electronic device package can also include a processor mounted on the package substrate. Additionally, the electronic device package can include a memory socket mounted on the package substrate and operably coupled to the processor. The memory socket can be operable to removably couple with a memory module and facilitate electrical communication between the processor and the memory module. A memory module can include a plurality of printed circuit boards (PCBs). Each PCB can have a bottom edge and a plurality of contact pads located about the bottom edge. Additionally, the memory module can include a memory device mounted on at least one of the plurality of PCBs and electrically connected to at least one of the pluralities of contact pads to facilitate electrically coupling the memory module with an external electronic component, such as a processor.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Applicant: Intel Corporation
    Inventors: Gregorio R. Murtagian, Kuang C. Liu, Sriram Srinivasan, Jeffory L. Smalley, Zhichao Zhang
  • Patent number: 10186497
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices. In one embodiment, an electrical contact includes a leg portion configured to extend in a first direction, a foot portion coupled with the leg portion, the foot portion having a surface that extends in a second direction that is substantially perpendicular to the first direction, the surface being configured to directly couple with solderable material to form a solder joint, a heel portion adjoining the leg portion and the foot portion, the heel portion having a profile shape, and a toe portion extending from the foot portion and disposed opposite to the heel portion, the toe portion having a profile shape that is symmetric with the profile shape of the heel portion. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Mark D. Summers, Kuang C. Liu
  • Publication number: 20180007791
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 4, 2018
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9832876
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9825387
    Abstract: Embodiments of the present disclosure are directed to a linear edge connector assembly and corresponding bolster plate features for receiving and securing a linear edge connector assembly. Embodiments of the disclosure are directed to a linear edge connector assembly that includes a grooved and indented receiver that can receive a spring loaded ball on the bolster plate. In embodiments, the linear edge connector assembly can include a magnetic element to create a magnetic attraction to magnetic elements on the bolster plate, such as a press-fit ball or a U-shaped hardstop. In some embodiments, the linear edge connector assembly includes a screw or push pin that can be received by a receiver on the bolster plate. The receiver can include a thread or friction fit receiver.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Jonathon Robert Carstens
  • Publication number: 20170288331
    Abstract: Embodiments of the present disclosure are directed to a linear edge connector assembly and corresponding bolster plate features for receiving and securing a linear edge connector assembly. Embodiments of the disclosure are directed to a linear edge connector assembly that includes a grooved and indented receiver that can receive a spring loaded ball on the bolster plate. In embodiments, the linear edge connector assembly can include a magnetic element to create a magnetic attraction to magnetic elements on the bolster plate, such as a press-fit ball or a U-shaped hardstop. In some embodiments, the linear edge connector assembly includes a screw or push pin that can be received by a receiver on the bolster plate. The receiver can include a thread or friction fit receiver.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Jonathon Robert Carstens
  • Publication number: 20170288330
    Abstract: Embodiments of the disclosure are directed to a linear edge connector assembly for connecting to a substrate diving board of a mother board. The linear edge connector assembly can include an electrical interface to electrically connect the contacts on the diving board to one or more conducts of a cable bundle. The linear edge connector assembly can also include a retaining force mechanism. The retaining force mechanism can include a torsional spring, a spring loaded hooking mechanism, or a spring loaded cam and lever. In some embodiments, the linear edge connector can include a notch to receive a latch connected to a bolster plate on the mother board.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: Feifei Cheng, Kuang C. Liu, Michael Garcia, Eric W. Buddrius, Kevin J. Ceurter, Anthony P. Valpiani, Jonathon Robert Carstens
  • Publication number: 20170229420
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices. In one embodiment, an electrical contact includes a leg portion configured to extend in a first direction, a foot portion coupled with the leg portion, the foot portion having a surface that extends in a second direction that is substantially perpendicular to the first direction, the surface being configured to directly couple with solderable material to form a solder joint, a heel portion adjoining the leg portion and the foot portion, the heel portion having a profile shape, and a toe portion extending from the foot portion and disposed opposite to the heel portion, the toe portion having a profile shape that is symmetric with the profile shape of the heel portion. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Mark D. Summers, Kuang C. Liu
  • Patent number: 9647363
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices. In one embodiment, an electrical contact includes a leg portion configured to extend in a first direction, a foot portion coupled with the leg portion, the foot portion having a surface that extends in a second direction that is substantially perpendicular to the first direction, the surface being configured to directly couple with solderable material to form a solder joint, a heel portion adjoining the leg portion and the foot portion, the heel portion having a profile shape, and a toe portion extending from the foot portion and disposed opposite to the heel portion, the toe portion having a profile shape that is symmetric with the profile shape of the heel portion. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Mark D. Summers, Kuang C. Liu
  • Patent number: 9615483
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Michael Garcia, Kuang C. Liu, Rajasekaran Swaminathan
  • Publication number: 20160183374
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Publication number: 20160087361
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices. In one embodiment, an electrical contact includes a leg portion configured to extend in a first direction, a foot portion coupled with the leg portion, the foot portion having a surface that extends in a second direction that is substantially perpendicular to the first direction, the surface being configured to directly couple with solderable material to form a solder joint, a heel portion adjoining the leg portion and the foot portion, the heel portion having a profile shape, and a toe portion extending from the foot portion and disposed opposite to the heel portion, the toe portion having a profile shape that is symmetric with the profile shape of the heel portion. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 24, 2016
    Inventors: Mark D. Summers, Kuang C. Liu
  • Publication number: 20160079150
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Michael Garcia, Kuang C. Liu, Rajasekaran Swaminathan