Patents by Inventor Kuang Chen

Kuang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11922754
    Abstract: An automatic dispensing device for use in storing and selectively dispensing electronic transmission devices, for example tire pressure monitoring system (TPMS) tire sensors. The dispensing device assists a user in determining the proper transmission device to be dispensed and programs or configures the transmission device in the dispenser prior to dispensing the programmed or configured transmission device to the user. When used for TPMS tire sensors, the dispenser determines the type of TPMS sensor to be programmed, programs the sensor with the proper communication protocol, and dispenses the programmed or configured sensor to the user for installation in the vehicle wheel and tire.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: March 5, 2024
    Assignee: ATEQ
    Inventors: Ermald Muca, Cheng-Kuang Chen, Grant Barnes
  • Patent number: 11923647
    Abstract: A conductive mechanism includes two bases, an inner conductive spring and an outer conductive spring. The two bases are opposite to each other. Each of the bases includes a surface and a partition wall protruding relative to the surface. The inner conductive spring is disposed at inner sides of the two partition walls of the two bases. The outer conductive spring is disposed at outer sides of the two partition walls of the two bases. At least one of two ends of each of the inner conductive spring and the outer conductive spring rotatably abuts against the surface of one of the bases.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Chung-Kuang Chen, Chih-Hung Ju, Guo-Hao Huang
  • Publication number: 20240068652
    Abstract: The present disclosure provides a connecting device and a lamp system. The connecting device is used to connect multiple lamps to form the lamp system. The connecting device includes a connecting element, a cover, and a shell. The cover is mounted on the connecting element and includes at least two first assembling members. The shell is detachably mounted on the cover. The shell includes a side wall, an opening, multiple gateways, and at least two second assembling members. The side wall surrounds a space. The opening and the gateways all are formed on a top of the side wall and communicate with the space. A portion of each of the lamps is received in one of the gateways. The second assembling members are disposed on the side wall and face each other in a radial line of the shell, and respectively engage with the first assembling members.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Chih-Hung JU, Cheng-Ang CHANG, Guo-Hao HUANG, Chung-Kuang CHEN
  • Publication number: 20240069619
    Abstract: A method, system, and article provide image processing with power reduction while using universal serial bus cameras.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: Ko Han Wu, Thiam Wah Loh, Kenneth K. Lau, Wen-Kuang Yu, Ming-Jiun Chang, Andy Yeh, Wei Chih Chen
  • Publication number: 20240072669
    Abstract: A power converter includes a high side switch, a low side switch, a low side driver, a loading detector, a configurable regulator and a high side driver. The low side driver generates a low side drive signal to control the low side switch. The configurable regulator generates a regulation voltage, a magnitude of which is greater when the loading detector detects that the power converter has light loading than when the loading detector detects that the power converter has heavy loading. The high side driver generates a high side drive signal that switches between the input voltage and the regulation voltage to control the high side switch.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Meng LAN, Yung-Chou LIN, Tuo-Kuang CHEN, Chih-Yang KANG
  • Publication number: 20240072411
    Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Applicant: Pegatron Corporation
    Inventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
  • Publication number: 20240071854
    Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chien-Li KUO, Kuo-Chio LIU
  • Publication number: 20240071950
    Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
  • Publication number: 20240061780
    Abstract: A computer-implemented method for allocating memory bandwidth of multiple CPU cores in a server includes: receiving an access request to a last level cache (LLC) shared by the multiple CPU cores in the server, the access request being sent from a core with a private cache holding copies of frequently accessed data from a memory; determining whether the access request is an LLC hit or an LLC miss; and controlling a memory bandwidth controller based on the determination. The memory bandwidth controller performs a memory bandwidth throttling to control a request rate between the private cache and the last level cache. The LLC hit of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be disabled and the LLC miss of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be enabled.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 22, 2024
    Inventors: Lide DUAN, Bowen HUANG, Qichen ZHANG, Shengcheng WANG, Yen-Kuang CHEN, Hongzhong ZHENG
  • Publication number: 20240056021
    Abstract: The present invention relates to an array solar power generation device, comprising a plurality of solar panels, a frame unit, a support unit and at least one reflecting device.
    Type: Application
    Filed: June 18, 2019
    Publication date: February 15, 2024
    Inventor: Kuei-Kuang Chen
  • Patent number: 11901188
    Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
  • Publication number: 20240045809
    Abstract: The present application discloses a computing system and an associated method. The computing system includes a memory, a master computing device and a slave computing device. The master computing device includes a memory controller and an input-output memory management unit (IOMMU). When the slave computing device accesses a first virtual address, and a first translation lookaside buffer (TLB) of the slave computing device does not store the first virtual address, the first TLB sends a translation request to the IOMMU. The IOMMU traverses page tables of the memory controller to obtain a first physical address corresponding to the first virtual address, selects and clears a first virtual address entry from a second TLB of the computing system according to a recent use time and a dependent workload of each virtual address entry to store the first virtual address and the first physical address.
    Type: Application
    Filed: December 13, 2022
    Publication date: February 8, 2024
    Inventors: LIDE DUAN, QICHEN ZHANG, SHIJIAN ZHANG, YEN-KUANG CHEN
  • Publication number: 20240045805
    Abstract: Core-aware caching systems and methods for non-inclusive non-exclusive shared caching based on core sharing behaviors of the data and/or instructions. In one implementation, the caching between a shared cache level and a core specific cache level can be based on physical page number (PPN) and core identifier sets for previous accesses to the respective physical page numbers. In another implementation, the caching between a shared cache level and a core specific cache level can be based on physical page number and core valid bit vector sets for previous accesses to the respective physical page numbers by each of the plurality of cores.
    Type: Application
    Filed: January 20, 2021
    Publication date: February 8, 2024
    Inventors: Lide DUAN, Guocai ZHU, Yen-kuang Chen, Hongzhong ZHENG
  • Patent number: 11894238
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Publication number: 20240039752
    Abstract: A mechanism is described for facilitating portable, reusable, and shareable Internet of Things-based services and resources according to one embodiment. A method of embodiments, described herein, includes selecting a recipe, wherein the recipe includes instructions associated with a first trigger to activate a first set of resources, the first set of resources and instructions correspond to a first category, accessing a second set of resources associated with a second trigger to activate the second set of resources, the second set of resources and instructions correspond to a second category of user preferences, the second category different from the first category, modify the recipe to replace a first resource block of the first set of resources with a second resource block of the second set of resources, and deploy the recipe at a computing device, the computing device receiving at least one of the first trigger or the second trigger.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 1, 2024
    Inventors: Shao-Wen Yang, Nyuk Kin Koo, Yen-Kuang Chen
  • Patent number: 11887360
    Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data captured by one or more sensors associated with a first device. Further, the processor comprises circuitry to: access the sensor data captured by the one or more sensors associated with the first device; determine that an incident occurred within a vicinity of the first device; identify a first collection of sensor data associated with the incident, wherein the first collection of sensor data is identified from the sensor data captured by the one or more sensors; preserve, on the memory, the first collection of sensor data associated with the incident; and notify one or more second devices of the incident, wherein the one or more second devices are located within the vicinity of the first device.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: January 30, 2024
    Assignee: Intel Corporation
    Inventors: Shao-Wen Yang, Eve M. Schooler, Maruti Gupta Hyde, Hassnaa Moustafa, Katalin Klara Bartfai-Walcott, Yen-Kuang Chen, Jessica McCarthy, Christina R. Strong, Arun Raghunath, Deepak S. Vembar
  • Patent number: 11886263
    Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 30, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Po-Jung Chou, Sheng-Wen Chen, Chung-Kuang Chen
  • Publication number: 20240028392
    Abstract: The present disclosure discloses a batch computing system and an associated method. The batch computing system includes a memory, a task manager and an inference computer. The memory stores a shared model parameter set common to a plurality of tasks that is generated by fine tuning a shared model and a task-specific parameter set of each task. The inference computer receives a plurality of task requests, derives a data length and a designated task of each task request, and enables the task manager to read a task-specific parameter set and a shared model parameter set corresponding to each task request. The inference computer further assigns task requests corresponding to the shared model to a plurality of computation batches, performs, in batch, the common computation of designated tasks in each batch computation, and performs task-specific computation operations of the designated tasks of each batch computation.
    Type: Application
    Filed: May 24, 2023
    Publication date: January 25, 2024
    Inventors: XUECHAO WEI, ZHE ZHOU, JIEJING ZHANG, SICHENG LI, YEN-KUANG CHEN, BIZHAO SHI
  • Publication number: 20240020123
    Abstract: The present application discloses a processor and a data operation method thereof. The processor includes: a first set of registers, a second set of registers and an execution unit. The execution unit is electrically connected to the first set of registers and the second set of registers, and configured to: convert data stored in the first set of registers from a first bit unit to a second bit unit, wherein the number of bits of the first bit unit is less than the number of bits of the second bit unit and the number of bits of the second bit unit is not an integer multiple of the number of bits of the first bit unit; and store the data in the second set of registers, wherein the number of registers of the second set of registers is greater than the number of registers of the first set of registers.
    Type: Application
    Filed: May 23, 2023
    Publication date: January 18, 2024
    Inventors: YANHENG LU, YEN-KUANG CHEN
  • Publication number: 20240020998
    Abstract: A character recognition method includes the stages as detailed in the following paragraph. An image is received, wherein the image is one in a plurality of consecutive images. A target object in the image is detected. Object information of the target object is defined according to the area ratio of the target object occupied in the image. Whether the target object in the image is the same as the target object in the previous image is determined according to the object information. Character recognition on the target object is performed to obtain a recognition result. The weighting score of the recognition result is calculated according to the object information and the recognition result. The weighting score of the recognition result of the target object in the consecutive images is accumulated until the weighting score is higher than a preset value, and the recognition result is output.
    Type: Application
    Filed: October 12, 2022
    Publication date: January 18, 2024
    Inventors: Chen-Chung LEE, Chia-Hung LIN, Chun-Hung CHEN, Chien-Kuo HUNG, Wen-Kuang CHEN, En-Chi LEE