Patents by Inventor Kuang-Chih Wang

Kuang-Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Patent number: 7449407
    Abstract: An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: November 11, 2008
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Patent number: 7253095
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: August 7, 2007
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Publication number: 20070076339
    Abstract: An air gap structure substantially reduces undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Application
    Filed: November 20, 2006
    Publication date: April 5, 2007
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Patent number: 7138329
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: November 21, 2006
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Publication number: 20060240867
    Abstract: A mobile phone with monitoring functions, a monitoring system and a monitoring method thereof are disclosed. The mobile phone monitoring system includes at least a mobile phone, a monitoring unit, a control unit and a predetermined abnormality reaction unit. The mobile phone serves as the mainbody of the monitoring system. The monitoring unit is used for capturing the signal data of a specified area. The control unit is used for generating a triggering signal in response to an abnormal situation. The predetermined abnormality reaction unit is used for generating a preset abnormal signal. The mobile phone monitoring system combines the mobility of a mobile phone with the monitor abnormality reaction of a monitoring system to substantially enhance the capability and feasibility of monitoring tasks.
    Type: Application
    Filed: August 23, 2005
    Publication date: October 26, 2006
    Inventors: Kuang-Chih Wang, Chih-Hsin Hsu
  • Publication number: 20060014388
    Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.
    Type: Application
    Filed: September 12, 2005
    Publication date: January 19, 2006
    Inventors: Water Lur, David Lee, Kuang-Chih Wang
  • Publication number: 20050263896
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Application
    Filed: July 11, 2005
    Publication date: December 1, 2005
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Patent number: 6943110
    Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: September 13, 2005
    Assignee: United Microelectronics, Corp.
    Inventors: Water Lur, David Lee, Kuang-Chih Wang
  • Publication number: 20050179139
    Abstract: A semiconductor device that includes cobalt-silicide based contacts is disclosed, as well as a process for making the same. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction on a silicon substrate. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor devices and processes.
    Type: Application
    Filed: April 8, 2005
    Publication date: August 18, 2005
    Inventors: Water Lur, David Lee, Kuang-Chih Wang
  • Publication number: 20050176248
    Abstract: A semiconductor device that includes cobalt-silicide based contacts is disclosed, as well as a process for making the same. Combinations of alloyed layers of Co—Ti—along with layers of Co—are arranged and heat treated so as to effectuate a silicide reaction on a silicon substrate. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor devices and processes.
    Type: Application
    Filed: April 8, 2005
    Publication date: August 11, 2005
    Inventors: Water Lur, David Lee, Kuang-Chih Wang
  • Patent number: 6917109
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: July 12, 2005
    Assignee: United Micorelectronics, Corp.
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Patent number: 6878627
    Abstract: A semiconductor device that includes cobalt-silicide based contacts is disclosed, as well as a process for making the same. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction on a silicon substrate. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor devices and processes.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: April 12, 2005
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, David Lee, Kuang-Chih Wang
  • Patent number: 6743721
    Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: June 1, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Water Lur, David Lee, Kuang-Chih Wang
  • Publication number: 20040094821
    Abstract: An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 20, 2004
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Publication number: 20040097065
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 20, 2004
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Publication number: 20040097013
    Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 20, 2004
    Inventors: Water Lur, David Lee, Kuang-Chih Wang, Ming-Sheng Yang
  • Publication number: 20030228745
    Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.
    Type: Application
    Filed: June 10, 2002
    Publication date: December 11, 2003
    Inventors: Water Lur, David Lee, Kuang-Chih Wang
  • Patent number: 6174813
    Abstract: A dual damascene process of manufacturing dual damascene structure comprising the steps of first providing a semiconductor substrate that already has an insulating layer formed thereon. Next, a trench and a via opening are formed within the insulating layer. In the subsequent step, a first glue layer, preferably a titanium layer, is formed over the trench and the via opening. Thereafter, photolithographic and etching operations are again used to remove a portion of the first glue layer in a region surrounding the trench. Consequently, a portion of the insulating layer is exposed while the trench and the via opening are still covered by the first glue layer. After that, a second glue layer, preferably a titanium nitride layer, is formed over the first glue layer and the insulating layer. Then, a metallic layer is formed over the second glue layer. The metallic layer completely fills the trench and the via opening. The second glue layer and the metallic layer have a polishing selectivity ratio of about 1:1.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: January 16, 2001
    Assignee: United Integrated Circuits Corp.
    Inventor: Kuang-Chih Wang
  • Patent number: 6066550
    Abstract: A method of improving selectivity between silicon nitride and silicon oxide. A pad oxide is formed on a substrate. Using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, a silicon nitride layer is formed on the silicon oxide layer. The silicon nitride is implanted by boron ions to transform into boron nitride. A conventional method is performed to form a shallow trench isolation.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: May 23, 2000
    Assignee: United Integrated Circuits Corp.
    Inventor: Kuang-Chih Wang