Abstract: A semiconductor structure with backside through silicon vias (TSVs) is provided in the present invention, including a semiconductor substrate with a front side and a back side, multiple dummy pads set on the front side, multiple backside TSVs extending from the back side to the front side, wherein a number of the dummy pads are connected with the backside TSVs while other dummy pads are not connected with the backside TSVs, and a metal coating covering the back side and the surface of backside TSVs and connected with those dummy pads that connecting with the backside TSVs.

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

Abstract: A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other.

Abstract: A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.

Abstract: A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.

Abstract: A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.

Abstract: A package structure is disclosed. The package structure includes a die; a substrate disposed corresponding to the die, wherein the substrate comprises a first dummy pad and a second dummy pad on a first surface of the substrate; and a first solder ball and a second solder ball on a second surface of the substrate and electrically connect the first dummy pad and the second dummy pad respectively.

Abstract: A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.

Abstract: A package structure is disclosed. The package structure includes a first die, a second die on the first die, and a substrate disposed corresponding to the first die. The first die includes a first die identification (ID) region defined thereon and a plurality of first through silicon vias (TSVs) in the first die ID region. The second die includes another first die identification (ID) region and a second die ID region defined thereon and a plurality of second TSVs in the another first die ID region and a plurality of third TSVs in the second die ID region, in which the second TSVs are electrically connected to the first TSVs in the first die.

Abstract: A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other.

Abstract: A package structure is disclosed. The package structure includes a die; a substrate disposed corresponding to the die, wherein the substrate comprises a first dummy pad and a second dummy pad on a first surface of the substrate; and a first solder ball and a second solder ball on a second surface of the substrate and electrically connect the first dummy pad and the second dummy pad respectively.

Abstract: A chip package is disclosed. The chip package comprises a chip, a plurality of bond pads, a plurality of connecting lines and a rigid cover. The chip has a plurality of recesses arranged along at least an edge of the chip and also has an active surface and a backside. The bond pads are disposed on the active surface and the bond pads are arranged to be corresponding to the recesses respectively. The connecting lines are disposed on surfaces of the recesses respectively at the edge of the chip. For each of the connecting lines, a first end of the connecting line is connected to one of the bond pads and a second end of the connecting line extends to the backside to be a terminal pad. The rigid cover is located on the active surface without covering the bond pads on the active surface.

Abstract: A chip packaging process includes providing a wafer, having an active surface and a backside. The wafer has a first chip area and a second chip area adjacent to the first chip area. The wafer has several first and second bond pads on the active surface in the first and second chip areas respectively. Several through holes are formed on the wafer. The through holes pass through the wafer and connect the active surface and the backside. The through. holes are arranged between the first chip area and the second chip area. Several connecting lines are formed on peripheral surfaces of the through holes. Each of the connecting lines has a first end portion extending on the active surface and a second portion extending on the backside. Each the first end portion is electrically connected to one of the first bond pads and one of the second bond pads.

Abstract: A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the passivation layer has a first opening exposing a bonding region of the bonding pad and a second opening exposing a probing region of the bonding pad, respectively.

Abstract: The chip package and the process thereof are disclosed. The chip package comprises a chip and a rigid cover. The chip has a plurality of bond pads formed thereon. The rigid cover is located on the chip and has a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.

Abstract: A chip packaging process includes providing a wafer, having an active surface and a backside. The wafer has a first chip area and a second chip area adjacent to the first chip area. The wafer has several first and second bond pads on the active surface in the first and second chip areas respectively. Several through holes are formed on the wafer. The through holes pass through the wafer and connect the active surface and the backside. The through. holes are arranged between the first chip area and the second chip area. Several connecting lines are formed on peripheral surfaces of the through holes. Each of the connecting lines has a first end portion extending on the active surface and a second portion extending on the backside. Each the first end portion is electrically connected to one of the first bond pads and one of the second bond pads.

Abstract: The chip package and the process thereof are disclosed. In the chip package, a rigid cover is disposed on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermal conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground, the electromagnetic interference (EMI) to the chip package can be reduced. It should be noted that the chip packaging process can form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.