CHIP PACKAGE AND PROCESS THEREOF
The chip package and the process thereof are disclosed. The chip package comprises a chip and a rigid cover. The chip has a plurality of bond pads formed thereon. The rigid cover is located on the chip and has a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.
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This application is a divisional application of, and claims the priority benefit of, U.S. application Ser. No. 10810,436 filed on Mar. 25, 2004. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention generally relates to a chip package and a process thereof, and more particularly to a chip package having a rigid cover on the active surface of the chip and a process thereof.
2. Description of Related Art
In the semiconductor industry, integrated circuit (IC) manufacturing includes 3 steps—design, process, and packaging. Chips are manufactured by the steps of making wafer, designing the circuit, making the mask, sawing the wafer and so on. Each chip is electrically connected to the external circuit via the bond pads on the chip. Then the insulating material is optionally used to package the chip. The purposes of packaging are to protect the chip from moisture, heat and noise, and to provide the electrical connection between the chip and the external circuit such as printed circuit board (PCB) or other carriers.
As the IC packaging technology advances, the package is getting smaller. Among the IC packaging types, chip scale package (CSP) is one of the package technologies that the length of the package is smaller than 1.2 times of the length of the chip inside the package, or (the chip area/package area) is smaller than 80% while the pitch of the pins of the package is smaller than 1 mm. Based on the material and the structures, CSP includes rigid interposer type, flex interposer type, custom lead frame type, wafer level type and so on.
Unlike the packaging technology for single chip, the wafer level package focuses on packaging wafer in order to simplify the chip packaging process. Hence, after the integrated circuits have been manufactured on the wafer, the whole wafer can be packaged. Then the wafer sawing can be performed to form a plurality of chips from the wafer.
SUMMARY OF THE INVENTIONAn object of the present invention is to provide a chip package having a better structural strength, thermal conductive efficiency, and anti-electromagnetic interference ability.
The present invention provides a chip package, comprising a chip and a rigid cover. The chip has a plurality of bond pads formed thereon. The rigid cover is located on the chip and has a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.
In a preferred embodiment, the chip package further comprises an adhesive layer disposed between the chip and the rigid cover, wherein the rigid cover is adhered to the chip via the adhesive layer.
In a preferred embodiment, the chip package further comprises a plurality of contacts electrically connected to the bond pads respectively.
In a preferred embodiment, the contacts include conductive bumps.
In a preferred embodiment, the contacts are connected to the PCB.
In a preferred embodiment, the heights of the contacts relative to a top surface of the chip are larger than the height of the rigid cover to the top surface.
In a preferred embodiment, the chip includes a redistribution layer on the chip to form the bond pads.
In a preferred embodiment, the material of the rigid cover includes a conducting material, an insulating material, or a transparent material.
In a preferred embodiment, the bond pads are disposed on the chip as an array.
In a preferred embodiment, the bond pads are disposed in an interior region of the chip.
According to the chip package and the process thereof, a rigid cover is disposed on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermal conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground of the chip package, the electromagnetic interference (EMI) to the chip package can be reduced. It should be noted that the chip packaging process could form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.
In the above first and second chip packages, the rigid covers completely cover the wafers. A plurality of contacts such as conductive bumps, is disposed on the bond pads respectively. Then the wafer is sawed to obtain independent chip packages. It should be noted that although the contacts can be formed before sawing the wafer, one may also choose to form the contacts on the contact pads of the PCB. Then the chip package can be connected to the PCB via these contacts.
The second embodiment uses a plurality of connecting lines to extend the bond pads to the backside of the chip and to form the terminal pads on the backside of the chip.
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The second embodiment uses a plurality of connecting lines to extend the bond pads to the backside of the chip and to form the terminal pads on the backside of the chip. Hence, when the chip is connected to the PCB, the active surface of the chip can be exposed. When the rigid cover is a transparent material, the chip package in the second embodiment can be applied in optical-electronic devices such as CMOS image sensor (CIS) and solar cell, or bio-chip.
In brief, the chip package and the process thereof dispose a rigid cover on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermally conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground of the chip package, the electromagnetic interference (EMI) to the chip package can be reduced. If the rigid cover is a transparent material, the chip package can be applied in optic-electric or bio devices. In addition, the chip packaging process can form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.
The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.
Claims
1. A chip package, comprising:
- a chip having a plurality of bond pads formed thereon; and
- a rigid cover located on the chip and having a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.
2. The chip package of claim 1 further comprising an adhesive layer disposed between the chip and the rigid cover, wherein the rigid cover is adhered to the chip via the adhesive layer.
3. The chip package of claim 1 further comprising a plurality of contacts electrically connected to the bond pads respectively.
4. The chip package of claim 3, wherein the contacts include conductive bumps.
5. The chip package of claim 3, wherein the contacts are connected to the PCB.
6. The chip package of claim 3, wherein the heights of the contacts relative to a top surface of the chip are larger than the height of the rigid cover to the top surface.
7. The chip package of claim 1, wherein the chip includes a redistribution layer on the chip to form the bond pads.
8. The chip package of claim 1, wherein the material of the rigid cover includes a conducting material, an insulating material, or a transparent material.
9. The chip package of claim 1, wherein the bond pads are disposed on the chip as an array.
10. The chip package of claim 1, wherein the bond pads are disposed in an interior region of the chip.
Type: Application
Filed: Apr 10, 2008
Publication Date: Aug 7, 2008
Applicant: UNITED MICROELECTRONICS CORP. (Hsinchu)
Inventors: Min-Chih Hsuan (Hsinchu), Kai-Kuang Ho (Hsinchu City), Kuo-Ming Chen (Hsinchu County), Kuang-Hui Tang (Kaohsiung County)
Application Number: 12/100,631
International Classification: H01L 23/498 (20060101);