Patents by Inventor Kuang-Yuan Hsu
Kuang-Yuan Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8441107Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.Type: GrantFiled: August 30, 2012Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang-Yuan Hsu
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Publication number: 20130099320Abstract: The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is formed in the first opening. A second metal gate electrode is formed the second opening while the blocking layer is in the first opening. The blocking layer is then removed from the first opening, and a first metal gate electrode formed. In embodiments, this provides for a device having a second gate electrode that includes a second work function layer and not a first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer.Type: ApplicationFiled: October 19, 2011Publication date: April 25, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20130102142Abstract: The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon.Type: ApplicationFiled: October 21, 2011Publication date: April 25, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Wei-Yang Lee, Meng-Hsuan Chan, Huang Ching Yu, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20130075827Abstract: A method for fabricating a semiconductor device including providing a semiconductor substrate having a first opening and second opening. A dielectric layer is formed on the substrate. An etch stop layer on the dielectric layer in the first opening. Thereafter, a work function layer is formed on the etch stop layer and fill metal is provided on the work function layer to fill the first opening.Type: ApplicationFiled: September 26, 2011Publication date: March 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20130049109Abstract: A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes.Type: ApplicationFiled: August 22, 2011Publication date: February 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20130040455Abstract: A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Hsuan CHAN, Wei-Yang LEE, Da-Yuan LEE, Kuang-Yuan HSU
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Publication number: 20130032900Abstract: Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.Type: ApplicationFiled: August 1, 2011Publication date: February 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao HOU, Wei-Yang LEE, Xiong-Fei YU, Kuang-Yuan HSU
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Patent number: 8367563Abstract: A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.Type: GrantFiled: October 7, 2009Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Hui Ouyang, Da-Yuan Lee, Kuang Yuan Hsu, Hun-Jan Tao, Xiong-Fei Yu
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Publication number: 20130026637Abstract: An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hao HOU, Peng-Soon LIM, Da-Yuan LEE, Xiong-Fei YU, Chun-Yuan CHOU, Fan-Yi HSU, Jian-Hao CHEN, Kuang-Yuan HSU
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Publication number: 20130020630Abstract: A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.Type: ApplicationFiled: July 21, 2011Publication date: January 24, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Da-Yuan Lee, Kuang-Yuan Hsu
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Patent number: 8357603Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.Type: GrantFiled: December 18, 2009Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Wen Chan, Hsueh Wen Tsau, Kuang-Yuan Hsu
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Publication number: 20120319192Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.Type: ApplicationFiled: August 30, 2012Publication date: December 20, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang-Yuan Hsu
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Patent number: 8334198Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: April 12, 2011Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hao Chen, Wei-Yang Lee, Wei-Yeh Tang, Xiong-Fei Yu, Kuang-Yuan Hsu
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Patent number: 8334197Abstract: The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.Type: GrantFiled: December 16, 2009Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Xiong-Fei Yu, Wei-Yang Lee, Matt Yeh
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Patent number: 8329546Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.Type: GrantFiled: August 31, 2010Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Hui Ouyang, Ming-Jie Huang, Shin Hsien Liao
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Publication number: 20120261758Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate having a first active region; a first gate structure over the first active region, wherein the first gate structure comprises a first interfacial layer having a convex top surface; a first high-k dielectric over the first interfacial layer; and a first gate electrode over the first high-k dielectric.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yang LEE, Xiong-Fei YU, Da-Yuan LEE, Kuang-Yuan HSU
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Publication number: 20120264281Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Hao CHEN, Wei-Yang LEE, Wei-Yeh TANG, Xiong-Fei YU, Kuang-Yuan HSU
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Patent number: 8283222Abstract: A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.Type: GrantFiled: August 23, 2011Date of Patent: October 9, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Yuan Hsu, Da-Yuan Lee, Wei-Yang Lee, Hun-Jan Tao
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Patent number: 8278173Abstract: A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.Type: GrantFiled: June 30, 2010Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang-Yuan Hsu
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Publication number: 20120217578Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.Type: ApplicationFiled: May 8, 2012Publication date: August 30, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Soon Lim, Meng-Hsuan Chan, Kuang-Yuan Hsu