Patents by Inventor Kuang-Yuan Hsu
Kuang-Yuan Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8193081Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.Type: GrantFiled: October 20, 2009Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Meng-Hsuan Chan, Kuang-Yuan Hsu
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Publication number: 20120049247Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Hui Ouyang, Ming-Jie Huang, Shin Hsien Liao
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Patent number: 8093117Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.Type: GrantFiled: January 14, 2010Date of Patent: January 10, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh Wen Tsau, Kuang-Yuan Hsu, Bor-Wen Chan
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Publication number: 20120001266Abstract: A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Chia-Pin Lin, Kuang- Yuan Hsu
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Publication number: 20110306196Abstract: A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.Type: ApplicationFiled: August 23, 2011Publication date: December 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuang-Yuan Hsu, Da-Yuan Lee, Wei-Yang Lee, Hun-Jan Tao
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Patent number: 8048810Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.Type: GrantFiled: January 29, 2010Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Wen Tsai, Jim Cy Huang, Shun Wu Lin, Li-Shiun Chen, Kuang-Yuan Hsu
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Publication number: 20110256731Abstract: A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.Type: ApplicationFiled: April 14, 2010Publication date: October 20, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Yang LEE, Xiong-Fei YU, Jian-Hao CHEN, Cheng-Hao HOU, Da-Yuan LEE, Kuang-Yuan HSU
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Publication number: 20110256682Abstract: A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O2 and/or O3. A second high-k dielectric layer is formed on the treated first high-k dielectric layer. A second treatment is performed on the second high-k dielectric layer. In an embodiment, the high-k dielectric layer forms a gate dielectric layer of a field effect transistor.Type: ApplicationFiled: April 15, 2010Publication date: October 20, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xiong-Fei Yu, Wei-Yang Lee, Da-Yuan Lee, Kuang-Yuan Hsu, Yuan-Hung Chiu, Hun-Jan Tao, Hongyu Yu, Wu Ling
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Patent number: 8008143Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method can include providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure.Type: GrantFiled: December 30, 2009Date of Patent: August 30, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Yuan Hsu, Da-Yuan Lee, Wei-Yang Lee, Hun-Jan Tao
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Publication number: 20110193180Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Hao Chen, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20110189847Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.Type: ApplicationFiled: January 29, 2010Publication date: August 4, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fang Wen Tsai, Jim C.Y. Huang, Shun Wu Lin, Li-Shiun Chen, Kuang-Yuan Hsu
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Publication number: 20110171820Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate. A dummy gate is formed over the substrate. A dielectric material is formed around the dummy gate. The dummy gate is then removed to form an opening in the dielectric material. Thereafter, a work function metal layer is formed to partially fill the opening. The remainder of the opening is then filled with a conductive layer using one of a polysilicon substitute method and a spin coating method.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsueh Wen Tsau, Kuang-Yuan Hsu, Bor-Wen Chan
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Publication number: 20110159678Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method can include providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuang-Yuan Hsu, Da-Yuan Lee, Wei-Yang Lee, Hun-Jan Tao
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Publication number: 20110147858Abstract: The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance.Type: ApplicationFiled: December 21, 2009Publication date: June 23, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Soon LIM, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20110151655Abstract: The present disclosure provides various methods of fabricating a semiconductor device. A method of fabricating a semiconductor device includes providing a semiconductor substrate and forming a gate structure over the substrate. The gate structure includes a first spacer and a second spacer formed apart from the first spacer. The gate structure also includes a dummy gate formed between the first and second spacers. The method also includes removing a portion of the dummy gate from the gate structure thereby forming a partial trench. Additionally, the method includes removing a portion of the first spacer and a portion of the second spacer adjacent the partial trench thereby forming a widened portion of the partial trench. In addition, the method includes removing a remaining portion of the dummy gate from the gate structure thereby forming a full trench. A high k film and a metal gate are formed in the full trench.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Bor-Wen Chan, Hsueh Wen Tsau, Kuang-Yuan Hsu
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Publication number: 20110143529Abstract: The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.Type: ApplicationFiled: December 16, 2009Publication date: June 16, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Da-Yuan Lee, Kuang-Yuan Hsu, Xiong-Fei Yu, Wei-Yang Lee, Matt Yeh
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Publication number: 20110089484Abstract: A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.Type: ApplicationFiled: October 20, 2009Publication date: April 21, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Soon Lim, Meng-Hsuan Chan, Kuang-Yuan Hsu
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Publication number: 20110081774Abstract: A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.Type: ApplicationFiled: October 7, 2009Publication date: April 7, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Matt Yeh, Hui Ouyang, Da-Yuan Lee, Kuang Yuan Hsu, Hun-Jan Tao, Xiong-Fei Yu
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Publication number: 20050282350Abstract: A method is provided for filling a trench or gap between a pair of semiconductor devices formed above a substrate. A liner is applied in a trench or gap between a pair of devices by atomic layer deposition to partially fill the trench or gap. The trench or gap is filled by a bulk fill process.Type: ApplicationFiled: June 22, 2004Publication date: December 22, 2005Inventors: You-Hua Chou, Joung-Wei Liou, Kuang-Yuan Hsu, Chih-Lung Lin, Cheng-Yuan Tsai