Patents by Inventor Kuei-Sheng Wu
Kuei-Sheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9123730Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connection unit providing a signal to the RF circuit.Type: GrantFiled: July 11, 2013Date of Patent: September 1, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin, Kuei-Sheng Wu, Chia-Fang Lin
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Patent number: 9024416Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.Type: GrantFiled: August 12, 2013Date of Patent: May 5, 2015Assignee: United Microelectronics Corp.Inventors: Chun-Hung Chen, Ming-Tse Lin, Chien-Li Kuo, Kuei-Sheng Wu
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Publication number: 20150041952Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.Type: ApplicationFiled: August 12, 2013Publication date: February 12, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Ming-Tse Lin, Chien-Li Kuo, Kuei-Sheng Wu
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Publication number: 20150014828Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.Type: ApplicationFiled: July 11, 2013Publication date: January 15, 2015Inventors: Chien-Li Kuo, Yung-Chang Lin, Ming-Tse Lin, Kuei-Sheng Wu, Chia-Fang Lin
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Patent number: 8922328Abstract: An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion.Type: GrantFiled: August 16, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Kuei-Sheng Wu, Ching-Hsiang Tseng, Chang-Chien Wong
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Publication number: 20140332952Abstract: A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the opening structure and covers the dielectric layer. The first and second conductive layer structures are electrically connected to the conductor post. A voltage difference is existed between the first and second conductive layer structures, such that a current is passing through the first conductive layer structure, the opening structure and second conductive layer structure. A resistance values is related to the voltage difference and the current. A dimension of the opening structure is 10 times greater than a dimension of the first and second conductive layer structures.Type: ApplicationFiled: May 9, 2013Publication date: November 13, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Li Kuo, Yung-Chang Lin, Chun-Ting Yeh, Kuei-Sheng Wu
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Publication number: 20140061855Abstract: A capacitor structure includes a first conductive structure, a dielectric structure, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode. The first conductive structure is disposed over a substrate. The dielectric structure is disposed over the substrate and partially enclosing the first conductive structure. The dielectric structure has a trench. A first surface of the first conductive structure is exposed through the trench of the dielectric structure. The first capacitor electrode is disposed on a bottom and a sidewall of the trench. The first capacitor electrode is electrically contacted with the first surface of the first conductive structure. The capacitor dielectric layer is disposed on a surface of the first capacitor electrode. The second capacitor electrode is disposed on a surface of the capacitor dielectric layer and filled in the trench.Type: ApplicationFiled: September 6, 2012Publication date: March 6, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chien-Li KUO, Kuei-Sheng WU, Ju-Bao ZHANG, Rui-Huang CHENG, Xing-Hua ZHANG, Hong LIAO
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Patent number: 8399318Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: GrantFiled: May 10, 2012Date of Patent: March 19, 2013Assignee: United Microelectronics Corp.Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Publication number: 20130043972Abstract: An electrical fuse structure includes a top conductive pattern having a top fuse and a top fuse extension portion, a bottom conductive pattern having a bottom fuse and a bottom fuse extension portion corresponding to the top fuse extension portion, and a via conductive layer positioned between the top fuse extension portion and the bottom fuse extension portion for electrically connecting the top fuse extension portion and the bottom fuse extension portion.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Inventors: Kuei-Sheng Wu, Ching-Hsiang Tseng, Chang-Chien Wong
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Publication number: 20120286390Abstract: An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse includes a top fuse length and the top fuse length is equal to or larger than a predetermined value. The bottom fuse includes a bottom fuse length larger than the top fuse length.Type: ApplicationFiled: September 8, 2011Publication date: November 15, 2012Inventors: Kuei-Sheng Wu, Ching-Hsiang Tseng, Chang-Chien Wong, Wai-Yi Lien
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Publication number: 20120228718Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: ApplicationFiled: May 22, 2012Publication date: September 13, 2012Inventors: Yung-Chang LIN, Kuei-Sheng Wu, Chang-Chien Wong
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Publication number: 20120225524Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: ApplicationFiled: May 10, 2012Publication date: September 6, 2012Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Patent number: 8227890Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: GrantFiled: December 18, 2009Date of Patent: July 24, 2012Assignee: United Microelectronics CorporationInventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Patent number: 8071437Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.Type: GrantFiled: November 19, 2009Date of Patent: December 6, 2011Assignee: United Microelectronics Corp.Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong, Ching-Hsiang Tseng
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Patent number: 8035191Abstract: A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed.Type: GrantFiled: December 2, 2008Date of Patent: October 11, 2011Assignee: United Microelectronics Corp.Inventors: Yung-Chang Lin, Kuei-Sheng Wu, San-Fu Lin, Hui-Shen Shih
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Patent number: 8035097Abstract: A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction.Type: GrantFiled: December 1, 2008Date of Patent: October 11, 2011Assignee: United Microelectronics Corp.Inventors: Chien-Li Kuo, Yung-Chang Lin, Kuei-Sheng Wu, Chien-Hsien Chen
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Patent number: 8026573Abstract: An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.Type: GrantFiled: December 15, 2008Date of Patent: September 27, 2011Assignee: United Microelectronics Corp.Inventors: Chien-Li Kuo, Yung-Chang Lin, Kuei-Sheng Wu, San-Fu Lin
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Publication number: 20110147853Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
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Publication number: 20110117710Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.Type: ApplicationFiled: November 19, 2009Publication date: May 19, 2011Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong, Ching-Hsiang Tseng
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Publication number: 20110074538Abstract: An electrical fuse structure is disclosed. The electrical fuse structure includes: a fuse element disposed on surface of a semiconductor substrate; an anode electrically connected to one end of the fuse element; and a cathode electrically connected to another end of the fuse element, wherein no silicide is formed on at least part of the cathode of the electrical fuse structure.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Inventors: Kuei-Sheng Wu, Chang-Chien Wong, Tzu-Chuan Huang