Patents by Inventor Kuen Chang

Kuen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210332193
    Abstract: Synthetic amino acid-modified polymers and methods of making the same and using the same are disclosed. The synthetic amino acid-modified polymers possess distinct thermosensitive, improved water-erosion resistant, and enhanced mechanical properties, and are suitable of reducing or preventing formation of postoperative tissue adhesions. Additionally, the amino acid-modified polymers can also be used as a vector to deliver pharmaceutically active agents.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 28, 2021
    Applicant: PRO-VIEW BIOTECH CO., LTD.
    Inventors: Yu-Chia CHANG, Yunn-Kuen CHANG, Wen-Yen HUANG, Ging-Ho HSIUE, Hsieh-Chih TSAI, Shuian-Yin LIN, Nai-Sheng HSU, Tzu-Yu LIN
  • Patent number: 10586735
    Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: March 10, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
  • Patent number: 10449343
    Abstract: This invention relates to a device, a system and a method for applying a volume of liquid to a treatment surface. The device includes a container for containing the liquid, a pump for extracting liquid from the container, an actuator for operating the pump, and a collapsible receptacle for accommodating extracted liquid.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 22, 2019
    Assignee: ACRUX DDS PTY LTD
    Inventors: Shu Kuen Chang, Alain Regard, Anastasios G Karahalios, Mark LaFever
  • Patent number: 10427754
    Abstract: A continuous derailleur of a bicycle contains: a drive shaft, a rotary shaft, a brake shaft, and a braking device. The rotary shaft is mounted on the drive shaft. The drive shaft includes a bevel gear member having a first bevel gear and a second bevel gear. The drive shaft includes a first pedal shaft, and the brake shaft includes a first interactive bevel gear and includes the braking device. The rotary shaft includes a second interactive bevel gear and a third interactive bevel gear, and the second interactive bevel gear and the third interactive bevel gear mesh with the second bevel gear of the bevel gear member. The continuous derailleur further contains an output bevel gear, and the output bevel gear is rotatably fitted on the drive shaft, hence the second interactive bevel gear and the third interactive bevel gear mesh with the output bevel gear.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 1, 2019
    Inventor: Kuen-Chang Lo
  • Patent number: 10354878
    Abstract: A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
  • Patent number: 10312379
    Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang, Ching-Chung Yang
  • Publication number: 20190006528
    Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.
    Type: Application
    Filed: July 27, 2017
    Publication date: January 3, 2019
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang, Ching-Chung Yang
  • Publication number: 20180297665
    Abstract: A continuous derailleur of a bicycle contains: a drive shaft, a rotary shaft, a brake shaft, and a braking device. The rotary shaft is mounted on the drive shaft. The drive shaft includes a bevel gear member having a first bevel gear and a second bevel gear. The drive shaft includes a first pedal shaft, and the brake shaft includes a first interactive bevel gear and includes the braking device. The rotary shaft includes a second interactive bevel gear and a third interactive bevel gear, and the second interactive bevel gear and the third interactive bevel gear mesh with the second bevel gear of the bevel gear member. The continuous derailleur further contains an output bevel gear, and the output bevel gear is rotatably fitted on the drive shaft, hence the second interactive bevel gear and the third interactive bevel gear mesh with the output bevel gear.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 18, 2018
    Inventor: Kuen-Chang LO
  • Patent number: 10068500
    Abstract: Color display systems are disclosed, wherein the color display system includes a main display unit and a secondary display unit. The main display unit can include a plurality of rotatable color selection pods where one side of the color selection pod displays a color(s) and the other side of the color selection pod includes receptacles that can hold color chips. The color selection pods are arranged in columns, and each column can represent a particular color family or color category. The secondary display unit can include a first sub-display and a second sub-display, with each sub-display displaying colors of particular categories or themes. The color display system can also include a central work center which can include a work table and rotating color display.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: September 4, 2018
    Assignee: The Sherwin-Williams Company
    Inventors: Jacqueline L. Jordan, Paul D. Cobb, Sara B. Frisk, Matthew A. Stiffler, Shu Kuen Chang, Jeewon Jung, J. Randolph Plemel, John Grimley, Michelle Ha, Anastasios G. Karahalios
  • Publication number: 20180197742
    Abstract: A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.
    Type: Application
    Filed: January 10, 2017
    Publication date: July 12, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
  • Publication number: 20180158738
    Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 7, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
  • Patent number: 9985129
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9947746
    Abstract: A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang
  • Publication number: 20180097104
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9922881
    Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: March 20, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
  • Publication number: 20180047809
    Abstract: A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 15, 2018
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang
  • Patent number: 9859417
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Publication number: 20170345926
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Application
    Filed: June 24, 2016
    Publication date: November 30, 2017
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: D857192
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 20, 2019
    Assignee: Merck Sharp & Dohme Corp.
    Inventors: Greg Burkett, Shu Kuen Chang, Angie Kim, Jin Ko, Scott Mackie, Philip G. Green, Sharad Gupta, Angela M. Amend Kwasnik, Christin L. O'Neill, Robert Stianchi, Witold Swiatek
  • Patent number: D870270
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 17, 2019
    Assignee: Merck Sharp & Dohme Corp.
    Inventors: Greg Burkett, Shu Kuen Chang, Angie Kim, Jin Ko, Scott Mackie, Philip G. Green, Sharad Gupta, Angela M. Amend Kwasnik, Christin L. O'Neill, Robert Stianchi, Witold Swiatek