Abstract: Introduced here are approaches to classifying traffic that comprises data packets. For each data packet, a classification engine implemented on a computing device can identify an appropriate class from amongst multiple classes using a lookup table implemented in a memory. The memory could be, for example, static random-access memory (SRAM) as further discussed below. Moreover, the classification engine may associate an identifier with each data packet that specifies the class into which the data packet has been assigned. For example, each data packet could have an identifier appended thereto (e.g., in the form of metadata). Then, the data packets can be placed into queues based on the identifiers. Each queue may be associated with a different identifier (and thus a different class).

Abstract: An epitaxial growth device is provided, which includes an induction coil and a reaction body, and the induction coil is disposed along a circumferential direction of the reaction body; and the reaction body includes a heating base and a plurality of trays, wherein the heating base includes a plurality of workspaces, the plurality of trays are disposed in the plurality of workspaces, respectively, and each of the plurality of trays is disposed in a corresponding workspace; wherein each of the plurality of trays is configured to support a substrate, and each of the plurality of trays is capable of independently rotating relative to the heating base.

Abstract: A connector for high density, high speed, and high performance electronic systems. The connector has a housing with a mating face and holding one or more rows of terminals. The connector has a first conductive member with a planar body. A broadside of the planar body faces the mating face of the housing. The connector can have a second conductive member with a planar body extending orthogonally to the planar body of the first conductive member. The first and second conductive members are coupled to intermediate portions of ground terminals in a same row from opposite sides. The first and second conductive members can operate in synergy to improve signal integrity performances in connectors designed for 64 Gbps and beyond, while conforming to a standard that constrains mating and mounting interfaces.

Abstract: Embodiments of apparatus and method for digital variable gain adjustment (DVGA) are disclosed. In an example, a baseband chip includes an unpacking module, a symbol recording module operatively coupled to the unpacking module, and a first variable gain adjusting (VGA) module operatively coupled to the symbol recording module. The unpacking module is configured to unpack a plurality of symbols from a first representation of pseudo floating-point numbers to a second representation of fixed-point numbers. The symbol recording module is configured to obtain a symbol parameter based on the unpacking. The first VGA module is configured to dynamically adjust gains of the plurality of symbols having the second representation based on the symbol parameter.

Abstract: Embodiments of apparatus and method for data plane management are disclosed. In one example, an apparatus for communication both uplink and downlink can include a plurality of downlink clusters, each downlink cluster including a downlink cluster processor configured to process three or more downlink data layers. The apparatus can also include a plurality of uplink clusters, each uplink cluster including an uplink cluster processor configured to process three or more uplink data layers. The apparatus can further include a controller configured to scale the plurality of downlink clusters and configured to scale the plurality of uplink clusters. Scaling the plurality of downlink clusters and the plurality of uplink clusters can include activating or deactivating one or more clusters of the plurality of downlink clusters, the plurality of uplink clusters, or both the plurality of downlink clusters and the plurality of uplink clusters.

Abstract: Embodiments of apparatus and method for implementing weighted overlap-and-add (WOLA) after digital gain adjustment are disclosed. In an example, an apparatus for wireless communication includes a baseband chip and a radio frequency (RF) chip including a digital front-end. The baseband chip is configured to generate a stream of orthogonal frequency-division multiplexing (OFDM) symbols and adjust gains of the stream of OFDM symbols. The baseband chip or the RF chip is configured to apply WOLA to the stream of OFDM symbols having the adjusted gains.

Abstract: A method includes: receiving, at a first layer of a protocol stack, multiple code blocks from a base station, the multiple code blocks is a portion of a transport block and is associated with an error rate; transmitting, to a second layer of the protocol stack, the multiple code blocks; and determining, at the second layer and based on the error rate, whether to (1) store the multiple code blocks in memory or (2) process the multiple code blocks. A method for saving power in a physical (PHY) layer-to-medium access (MAC) layer interface and a network device, and a system are also provided.

Abstract: A configurable electrical connector. The connector has a housing body, a tower extending from the housing body and beyond a mating face, and a latch movably coupled to the housing body and/or tower. The tower is configurable according to a mating component. The tower can be a tower portion formed with the housing body. The tower can include an extender, with a lower portion disposed inside the tower portion and an upper portion disposed on the tower portion. The extender has an opening through which the latch can pass for engaging a mating component at the locked position. Such a configuration enables the connector to reliably hold a card taller than a standard card (e.g., according to DDR5 or below), and therefore enable the connector to be compatible with both standard cards and tall cards so as to support different storage capacities and data rates.

Abstract: A device and process for electrochemical treatment of wastewater with a screening current collector-based flow anode are provided. The device includes: a shell, where an interior of the shell is a cavity structure, and the shell is provided with a water inlet and a water outlet; a screening current collector structure, where the screening current collector structure includes a screening anode current collector and a cathode current collector, a cathode/anode separator is provided between the screening anode current collector and the cathode current collector, and the screening anode current collector and the cathode current collector each are connected to an external circuit; an anode cell and a cathode cell, where the anode cell and the cathode cell are formed through division of the cavity structure, and an electrolyte is provided in each of the anode cell and the cathode cell; and a flow anode suspended in the anode cell.

Abstract: Embodiments of apparatus and method for generating waveforms for self-testing of radio frequency (RF) chips are disclosed. In an example, an RF chip includes an RF front-end and a digital front-end. The digital front-end includes an inverse fast Fourier transform (IFFT) module configured to generate at least one M-point IFFT sample, where M is a positive integer, and an IFFT sample transformation module configured to generate an L-point IFFT testing signal based on the at least one M-point IFFT sample. L is a positive integer greater than M and the L-point IFFT testing signal is configured to test a function of the RF chip.

Abstract: A connector for economic and reliable operation of systems, such as systems having tall cards. The connector has a housing body, a tower extending from an end of the housing body and beyond a position that a notch of a standard card would be in a height direction, and a latch configured to cooperate with tall cards. The tower can have a first portion extending from the end of the housing body and a second portion coupled to the first portion. The latch can have a first member pivotable about an end of a second member so as to move the second member up and down when the latch moves between a locked position and an unlocked position. Such a configuration enables the connector to provide reliable connections for tall cards, while compatible with physical requirements of industry standards, for example, in length/width directions.

Abstract: A connector for high density, high speed, and high performance electronic systems. The connector has terminals held in a housing. Each terminal has a mating end, a mounting end, and an intermediate portion inbetween. A pair of cuts are disposed on opposite sides of the mounting end such that the mounting end is narrower than the intermediate portion. Each mounting end has a flat surface configured for a solder ball to be attached thereto and narrower than a diameter of the solder ball. This enables the solder ball to be reliably mounted to a contact pad on a circuit board that sized smaller than the solder ball. The contact pad can have a round shape such that a conductive trace can extend in any direction therefrom, which provides flexible routing. Such a configuration meets signal integrity requirements in connectors designed for 64 Gbps and beyond, while conforming to a standard that constrains mating and mounting interfaces.

Abstract: A connector for high density, high speed, and high performance electronic systems. The connector has multiple slots, each of which can receive a card. Terminals disposed on opposite sides of each slot connect the card inserted therein to a motherboard on which the connector is mounted. Each slot has a latch disposed at an end for retaining the card inserted therein when the latch is locked and releasing the card from the slot when the latch is unlocked. The connector has a reinforcing members configured to enhance the mechanical strength of the housing. Terminal tails are configured for solder ball attachments such that the terminals of adjacent slots are disposed closer. The tails are also configured such that a smaller solder area is needed on the motherboard. Such configurations improve signal integrity at higher speed and increases the tolerance of errors in the manufacturing process.

Abstract: A roll-type device for electrochemical recovery of ammonia is provided, including: a central tube and a tubular shell, where a hydrophobic gas membrane and an anion-exchange membrane (AEM) are sequentially wound around the central tube; a first porous flexible electrode and a first guide liner are sequentially wound at an inner side of the hydrophobic gas membrane, and a second porous flexible electrode and a second guide liner are sequentially wound at an inner side of the AEM; an inner side wall of the hydrophobic gas membrane, an outer wall of the central tube, an outer side wall of the AEM, and the tubular shell enclose a closed first electrode liquid flow chamber; and an inner side wall of the AEM, an outer wall of the central tube, an outer side wall of the hydrophobic gas membrane, and the tubular shell enclose a closed second electrode liquid flow chamber.

Abstract: A connector for use with high-speed signals. The connector has a housing, which includes conductive elements held in a row by a housing. Each conductive element includes a thinner portion and a thicker portion. The conductive elements are configured to make contact with a mating component at the thicker portions. The thinner portions are closer to mating ends of respective conductive elements than respective thicker portions. The housing is configured to provide voids selectively disposed underneath the conductive elements. Such a configuration increases impedances for the conductive elements at locations that would otherwise have lower impedance and therefore reduces impedance variations along signal transmission paths. Such a configuration can also reduce stub size and therefore reduce insertion loss. Such a configuration meets signal integrity requirements in connectors designed for 64 Gbps and beyond, while conforming to a standard that constrains mating and mounting interfaces.

Abstract: A robust electrical connector is provided. The connector includes a housing body, conductive elements held by the housing body, and a slot extending in the housing body and configured to receive a mating component. The housing body has a mating face and a mounting face opposite the mating face. The conductive elements include mating portions curving into the slot and configured to mate with the mating component, and mounting portions extending out of the mounting face. The connector includes a tower extending from an end of the housing body, and a latch pivotably connected to the tower so as to secure the mating component in the slot at a locked position. The tower includes a base portion extending from an end of the housing body, and a cover portion disposed on the base portion. Such a configuration reduces the risk that the tower cracks during operation.

Abstract: Connectors for use with high-speed signals. Mating connectors may include interlocking components that control the mated position of the connectors such that wipe distance can be reduced. These components may be compact such that they can be integrated into connectors with standardized exterior dimensions. They may be integrated into mating guides of the mating connectors. For one of the mating connectors, such a component may be a locking member disposed in and curving out of its guide such that the locking member mates with a matching feature of a component in the guide of the other connector. As the connectors are secured by these components, the conductive elements may be shorter than the lengths required by standards, which reduces the stub and therefore increases signal integrity. Such a configuration provides higher signal integrity at higher speeds, while conforming to standards that constrain mating and mounting interfaces.

Abstract: Surface mount card edge connectors and compact systems using such connectors are provided. A connector has a housing holding conductive elements with a mating face and a mounting face configured to face a side surface of a board. Each conductive element comprises a mating contact portion and a mounting tail extending beyond the mounting face and having an end surface configured to be mounted to a surface pad on a surface of the board. The connector has one or more board locks. Each board lock has a body portion disposed in the housing and a mounting portion having an end surface parallel to the end surfaces of the mounting tails of the conductive elements. Such a configuration enables connectors mounted to opposite sides of a board to be aligned such that a system with these connectors may be more compact.

Abstract: A card edge connector with reduced height that operates reliably. The connector has a housing with a slot extending toward a mounting face. An electronic card can be inserted into the slot until an edge of the card is in a seating plane. The connector has a latch pivotally connected to the housing which may be rotated to eject the card. A reinforcing member may be disposed in the latch with a foot extending between the edge of the card and the mounting face such that, when the latch is rotated, the foot may press against the edge of the card to eject the card. The reinforcing member is both mechanically stronger and thermally more conductive than the latch. Such a configuration enables the seating plane to be closer to the mounting face than that required to meet industry standards.

Abstract: Embodiments of apparatus and method for transition smoothing implementation on a stream of data are disclosed. In an example, a system on chip (SoC) for wireless communication includes a digital front-end. The digital front-end is configured to obtain a stream of data having one carrier or multi-carriers. The stream of data is divided into a plurality of blocks. The digital front-end is also configured to adjust a gain of the stream of data based on a predetermined frequency corresponding to a length of each of the plurality of blocks. The digital front-end is also configured to append a ramp-down tail sequence to a first block of the stream of data after a last sample of the first block, and generate a ramp-up head sequence for a second block immediately after the first block, based on a head sequence of the second block.