Abstract: An example apparatus includes a media management superblock component configured to determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks; compare the quantity of bad blocks to a bad block criteria; and write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria. The use of the superblock with a particular quantity of bad block minimizes yield loss for non-use of partial superblocks.

Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

Abstract: Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: Described are systems and methods for performing memory programming operations in the overwrite mode. An example memory device includes: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: responsive to identifying a first data item to be stored by a portion of the memory array, causing a first memory programming operation to be performed to program, to a first target threshold voltage, a set of memory cells included by the portion of the memory array; and responsive to identifying a second data item to be stored by the portion of the memory array, causing a second memory programming operation to be performed to program the set of memory cells to a second target threshold voltage exceeding the first target threshold voltage.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: Methods, systems, and devices for status information retrieval for a memory device are described. In some examples, a memory device may include a set of status registers, each of which may be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information along with an indication of one or more particular status registers from which to output status information in response to the command. In response to the command and indication, the memory device may output status information from any quantity of status registers, including any type of status information, in a single stream or burst.

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Abstract: An apparatus can include a media management superblock component. The media management superblock component can determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component can compare the quantity of bad blocks to a bad block criteria. The media management superblock component can write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Abstract: Methods for operating a memory device can include monitoring communications from a host device for a notification that a battery of the host device has entered a charging state and performing a background operation of the memory device responsive to receiving this notification. The notification can be an added functionality incorporated into a standardized interface.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

Abstract: A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

Abstract: An apparatus includes a media management superblock component. The media management superblock component determines that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component compares the quantity of bad blocks to a bad block criteria. The media management superblock component writes host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.

Abstract: An apparatus includes a media management superblock component. The media management superblock component determines that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component compares the quantity of bad blocks to a bad block criteria. The media management superblock component writes host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.

Abstract: A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating con

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.