Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

Abstract: A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.

Abstract: An apparatus is described. The apparatus includes a memory controller having a network interface and a channel interface. The channel interface is to send read, write and refresh commands into a region of a memory. The network interface is to receive memory access requests from a network, wherein the memory requests target the region of the memory. The memory requests are sent into the network by one or more host interfaces. The memory controller has bank refresh logic circuitry. The memory controller has signaling logic circuitry to send a back pressure signal to the one or more host interfaces. The back pressure signal identifies a bank of the region of the memory that is about to be refreshed by the bank refresh logic circuitry. The back pressure signal is to inform the one or more host interfaces that any memory requests that target the bank will not be serviced by the region of memory before the bank begins to be refreshed.

Abstract: A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The memory device includes a memory array to store data and prefetches data bits and error checking and correction (ECC) bits from the memory array for a memory access operation. The memory device includes internal ECC hardware to apply ECC, with a first group of a first half the data bits checked by a first half of the ECC bits in parallel with a second group of a second half of the data bits checked by a second half of the ECC bits.

Abstract: A system can predict what pages of memory the system should offline based on identification of how correctable error patterns correlate to the memory architecture. The failure prediction can account for the circuit-level architecture of the memory rather than the mere number or frequency of correctable errors. A controller correlates the hardware configuration of the memory with historical error data, and generates an estimate of pages for a host operating system (OS) to offline based on predicting uncorrectable errors (UEs).

Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

Abstract: A memory system has a configurable mapping of address space of a memory array to address of a memory access command. A controller provides command and enable information specific to a memory device. The command and enable information can cause the memory device to apply a traditional mapping of the command address to the address space, or can cause the memory device to apply an address remapping to remap the command address to different address space.

Abstract: A memory system has a configurable mapping of address space of a memory array to address of a memory access command. In response to a memory access command, a memory device can apply a traditional mapping of the command address to the address space, or can apply an address remapping to remap the command address to different address space.

Abstract: A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The ECC for an N/2-bit channel is simpler than the ECC for N bits, and thus, each N/2-bit portion can be separately correctable when treated as two N/2-bit portions. The memory device can include an additional hardware for the application of ECC to the channel as two sub-channels. For example, the memory device can include an additional subarray to store ECC bits for the internal ECC to enable the application of ECC to two sub-channels of the N-bit channel. The memory device can include an additional driver to access the additional subarray when applied.

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

Abstract: For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.

Abstract: A memory is described. The memory includes row buffer circuitry to store a page. The page is divided into sections, wherein, at least one of the sections of the page is to be sequestered for the storage of meta data, and wherein, a first subset of column address bits is to: 1) define a particular section of the page, other than the at least one sequestered sections of the page, whose data is targeted by a burst access; and, 2) define a field within the at least one of the sequestered sections of the page that stores meta data for the particular section.

Abstract: Methods and apparatus for lifetime telemetry on memory error statistics to improve memory failure analysis and prevention. Memory error information corresponding to detected correctable errors and uncorrectable memory errors are monitored, with the memory error information identifying an associated DRAM device in an associated DIMM. Corresponding micro-level error bits information from the memory error information is decoded and Micro-level Error Statistic Indicators (MESIs) are generated. Information associated with the MESIs from DRAM devices on the DIMMs are periodically written to persistent storage on those DIMMs. The MESIs for a given DIMM are updated over the lifetime of the DIMM.

Abstract: A memory chip is described. The memory chip includes row hammer threat detection circuitry. The memory chip includes an output. The memory chip includes backpressure signal generation circuitry coupled between the row hammer detection circuitry and the output. The backpressure signal generation signal is to generate a backpressure signal to be sent from the output in response to detection by the row hammer threat detection circuitry of a row hammer threat.

Abstract: A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.

Abstract: A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.