Patents by Inventor Kulwant M. Pandey

Kulwant M. Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030061375
    Abstract: A method and system for extensions to earlier patents dealing with the implementation of the InterSystem Channel (ISC) link architecture. First, it describes hardware state machines that handle all valid link messaging sequences without any processor involvement. These state machines also process larger commands and responses that may be divided into multiple frame segments. Finally, the missing frame detection is expanded for the multi frame segment commands and responses.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 27, 2003
    Applicant: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Patent number: 6442613
    Abstract: Controlling the flow of information between senders and receivers across links being used as channels. In one example, a self-timed interface link is adapted to be used as a channel. Such an interface is referred to as an integrated cluster bus. The flow control for the integrated cluster bus includes, for instance, a Data Request packet that indicates to the transmitter of data that it can now send the data; a continue indicator that specifies that more data is to follow; and a sequence indicator that is used to determine if a particular message is in proper sequence order. The integrated cluster bus does not require large data buffers and offers low latency messaging.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Publication number: 20010030943
    Abstract: Controlling the flow of information between senders and receivers across links being used as channels. In one example, a self-timed interface link is adapted to be used as a channel. Such an interface is referred to as an integrated cluster bus. The flow control for the integrated cluster bus includes, for instance, a Data Request packet that indicates to the transmitter of data that it can now send the data; a continue indicator that specifies that more data is to follow; and a sequence indicator that is used to determine if a particular message is in proper sequence order. The integrated cluster bus does not require large data buffers and offers low latency messaging.
    Type: Application
    Filed: June 20, 2001
    Publication date: October 18, 2001
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Publication number: 20010025317
    Abstract: Controlling the flow of information between senders and receivers across links being used as channels. In one example, a self-timed interface link is adapted to be used as a channel. Such an interface is referred to as an integrated cluster bus. The flow control for the integrated cluster bus includes, for instance, a Data Request packet that indicates to the transmitter of data that it can now send the data; a continue indicator that specifies that more data is to follow; and a sequence indicator that is used to determine if a particular message is in proper sequence order. The integrated cluster bus does not require large data buffers and offers low latency messaging.
    Type: Application
    Filed: June 5, 2001
    Publication date: September 27, 2001
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Patent number: 5610945
    Abstract: A system and method for asynchronously receiving data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. The transceivers for each member of the parallel bus examine the received bit stream to extract frames and continuous sequences. For each member of the parallel bus there are independent receive buffers, and these buffers are controlled by independent states. The states inhibit erroneously generated frames from corrupting the contents of the receive buffers and inhibit the loading of the buffers after errors on the link. These states also control the loading of the receive buffers after retransmission of a buffer area.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Joseph M. Hoke, Kulwant M. Pandey
  • Patent number: 5559963
    Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups can be prematurely ended on any 256 byte block boundary for several purposes, and all the frames of a given group must contain the same number of information field data words. Allowing frame groups to be ended on arbitrary block boundaries allows their transmission to start before all of the information field for the frame group has been received from a shared main processor storage. This capability of ending frame groups also allows high priority frame groups to interrupt the transmission of a relatively long data frame. Finally, the capability to end the frame group protects the information field of a stalled frame group since the CRC is sent and the idle sequence is resumed.
    Type: Grant
    Filed: November 4, 1993
    Date of Patent: September 24, 1996
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, Joseph M. Hoke, Kulwant M. Pandey