Abstract: Some data storage devices have a plurality of memory dies that can be read in parallel for certain types of read requests. Read requests pertaining to a garbage collection operation are often generated sequentially and, thus, are not eligible for parallel execution in the memory dies. In an example data storage device presented herein, such read requests are consolidated and sent to the memory for execution in parallel across the memory dies.

Abstract: Examples of the present disclosure describe systems and methods for unifying local channels with Over-the-Top (OTT) services (e.g., Internet-streaming media services). In one example aspect, a location is determined. Based on the determined location, a list of local channels available for broadcast in the geographic area is retrieved. The list of local channels is then compared to a list of channels offered via at least one OTT service. Based on the comparison with the OTT service channel offering, a subset of available local channels may be determined. The electronic programming guide (EPG) data and other programming metadata associated with the local channels may be downloaded and provided to the OTT service. The local channels, along with the EPG data and programming metadata, may be merged with the OTT service so that the local channels may be streamed via the OTT service.

Abstract: Link data is stored in a distributed link descriptor memory (“DLDM”) including memory instances storing protocol data unit (“PDU”) link descriptors (“PLDs”) or cell link descriptors (“CLDs”). Responsive to receiving a request for buffering a current transfer data unit (“TDU”) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

Abstract: An example apparatus comprises memory, first instructions, and programmable circuitry to be programmed by the first instructions to associate a first portion of metadata with a first category, the metadata corresponding to a cloud resource of a cloud account, associate a second portion of the metadata with a second category, and determine a template based on the first portion being greater than the second portion, the template associated with the first category, the template including second instructions to define a target state to be enforced on the cloud account.

Abstract: A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.

Abstract: A recirculation system for recirculating intestinal content within an intestinal tract of a subject including a recirculation pathway extending from a distal portion of the intestinal tract to a proximal portion of the intestinal tract forming a recirculation loop for recirculating the intestinal content through the proximal portion of the intestinal tract to increase nutrient absorption from the intestinal content. An externally controllable valve is disposed in the recirculation pathway for controlling flow of intestinal content through the recirculation pathway.

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N?1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N?1 number of redundant flip-flops is observed through the functional path to determine faults.

Abstract: A block-based storage system hosts logical volumes that are implemented via multiple replicas of volume data stored on multiple resource hosts in different failure domains. Also, the block-based storage service allows multiple client computing devices to attach to a same given logical volume at the same time. In order to prevent unnecessary failovers, a primary node storing a primary replica is configured with a health check application programmatic interface (API) and a secondary node storing a secondary replica determines whether or not to initiate a failover based on the health of the primary replica.

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N-1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N-1 number of redundant flip-flops is observed through the functional path to determine faults.

Abstract: An integrated circuit device (100) and method comprising an IC chip (102) having metal interconnect levels (M1-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect (110) overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect (110) having a via (112) connected to a first element (306a) of the last copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), the via coupled between the copper conductive structure (118) and the first element (306a).

Abstract: The following relates generally to systems and methods of transesophageal echocardiography (TEE) automation. Some aspects relate to a TEE probe with ultrasonic transducers on a distal end of the TEE probe. In some implementations, if a target is in a field of view (FOV) of the ultrasonic transducers, an electronic beam steering of the probe is adjusted; if the target is at an edge of the FOV, both the electronic beam steering and mechanical joints of the probe are adjusted; and if the target is not in the FOV, only the mechanical joints of the probe are adjusted.

Abstract: Embodiments identify a station that rotates an over the air station address. As address rotation was not originally designed into wireless networks, the rotation can introduce communication challenges for the station. The embodiments derive that traffic referencing two different over the air station addresses are associated with a single common station. This is accomplished by determining a similarity between properties of two sets of traffic. A first set of traffic references the first over the air station address and a second set of traffic references the second over the air station address. If the properties common across the two sets of traffic indicate sufficient similarity, the embodiments determine that both sets of traffic are associated with a single device. Network configuration of the device is then adjusted based on the determination.

Abstract: A method for service gap mitigation via tilt recommendation may include: identifying a candidate cell; generating boundaries of a service gap; determining a best server plot of the candidate cell; determining geo-located samples of the candidate cell; categorizing the candidate cell based on the boundaries of the service gap and at least one of the best server plot or the geo-located samples; and calculating an electronic tilt based on the categorization.

Abstract: A method of screen sharing include receiving, by a first server device and from a user device, device information corresponding to the user device, generating, by the first server device, a device identifier (ID) based on the device information, receiving, by the first server device and from the user device, a request for a token, generating, by the first server device, a token based on the device ID, and sending, by the first server device, the token to the user device.

Abstract: Methods and systems for optimizing antenna tilt in a cell site of a radio access network (RAN), the system includes: a memory storing instructions; and a processor configured to execute the instructions to: obtain input data for a source cell and for neighboring cells thereof at a plurality of predetermined geolocations; determine an overlap percentage from the input data obtained at the plurality of predetermined geolocations; determine, for the source cell, at least one TA percentage for at least one distance range from a center of the source cell; determine, based on the determined overlap percentage and the determined at least one TA percentage, that the source cell is outside a predetermined cell coverage area; and recommend, based on the determining that the source cell is outside the predetermined cell coverage area, adjustment of the antenna tilt for the source cell to meet the predetermined cell coverage area.

Abstract: Provided are a system and method of decongesting a highly utilized cell within a sector of a wireless telecommunications network. The method includes receiving a set of reference samples taken from a plurality of points within the wireless telecommunications network within a predetermined time period, calculating, based on the set of reference samples, a first data volume comprising a sum of a total data volume for all highly utilized cells within the sector containing the highly utilized cell, calculating, based on the set of reference samples, a first total expected traffic offload value, determining whether the first total expected traffic offload value is greater than a predetermined percentage of the first data volume, and based on determining that the first total expected traffic offload value is greater than the predetermined percentage of the first data volume, generating an output for decongesting the cell.

Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

Abstract: An acoustic imaging apparatus and method receive a sensor signal from a passive sensor disposed on a surface of an intervention device which is disposed in an area of interest, wherein the passive sensor is located at a fixed distance from the tip of the intervention device. A processor is configured to ascertain an estimated range of locations of the tip of the intervention device in an image plane by using the sensor signal and an estimated effective distance, projected onto the image plane, from the passive sensor to the tip of the intervention device.