Patents by Inventor Kumiko Takikawa

Kumiko Takikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050101282
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Application
    Filed: December 16, 2004
    Publication date: May 12, 2005
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Patent number: 6847108
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: January 25, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Patent number: 6826388
    Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
  • Publication number: 20040178497
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Application
    Filed: March 30, 2004
    Publication date: September 16, 2004
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Patent number: 6768192
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Publication number: 20040137941
    Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
    Type: Application
    Filed: December 23, 2003
    Publication date: July 15, 2004
    Applicants: Renesas Technology Corp., TTPCom Limited
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
  • Publication number: 20040137853
    Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
    Type: Application
    Filed: December 23, 2003
    Publication date: July 15, 2004
    Applicants: Renesas Technology Corp., TTPCom Limited
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa
  • Publication number: 20040057173
    Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.
    Type: Application
    Filed: September 22, 2003
    Publication date: March 25, 2004
    Applicant: HITACHI, LTD.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Masumi Kasahara
  • Publication number: 20040021208
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 5, 2004
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Patent number: 6665159
    Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: December 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Masumi Kasahara
  • Patent number: 6639310
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: October 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Patent number: 6624509
    Abstract: In a differential low-noise amplifier built in a semiconductor integrated circuit for a dual-band wireless transceiver, impedance components of wire bonding and package that occur in emitters are reduced and a gain is improved. Ground pins of amplifiers of the differential amplifier forming a pair are arranged adjacent to each other. Input pins and ground pins of the same amplifier are arranged adjacent to each other. Signals of the adjacent pins are allowed to have inverse phases, and trans-coupling between the pins is utilized so as to reduce impedance of the transistor emitters.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: September 23, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Satoshi Kayama, Yuichi Saito, Norio Hayashi
  • Publication number: 20020079569
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Application
    Filed: February 27, 2002
    Publication date: June 27, 2002
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Patent number: 6407449
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from a end of the pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: June 18, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Publication number: 20020053729
    Abstract: In a differential low-noise amplifier built in a semiconductor integrated circuit for a dual-band wireless transceiver, impedance components of wire bonding and package that occur in emitters are reduced and a gain is improved. Ground pins of amplifiers of the differential amplifier forming a pair are arranged adjacent to each other. Input pins and ground pins of the same amplifier are arranged adjacent to each other. Signals of the adjacent pins are allowed to have inverse phases, and trans-coupling between the pins is utilized so as to reduce impedance of the transistor emitters.
    Type: Application
    Filed: July 25, 2001
    Publication date: May 9, 2002
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Satoshi Kayama, Yuichi Saito, Norio Hayashi
  • Publication number: 20010015676
    Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 23, 2001
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Yoshiyasu Tashiro
  • Publication number: 20010015881
    Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 23, 2001
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Masumi Kasahara
  • Patent number: 5157660
    Abstract: A communication system including a plurality of portable terminal apparatuses each capable of calling a partner terminal apparatus via a radio channel and a plurality of fixed terminal apparatuses each being connected via an ISDN interface to a time-division switch and each being connectable to the portable terminal in which when two portable terminals having an established cell are respectively attached to two fixed terminal apparatuses arbitrarily selected, the state of the call is automatically transferred to the two fixed terminal apparatuses so that the speech can be achieved between the fixed terminal apparatuses without conducting another call establishing procedure.
    Type: Grant
    Filed: September 21, 1990
    Date of Patent: October 20, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Kuwahara, Nobuo Tsukamoto, Kumiko Takikawa, Yuji Sakamoto, Shirou Tanabe
  • Patent number: 5128981
    Abstract: This invention proposes a radio communication system including a plurality of radio terminals, a relay apparatus (including a plurality of base stations and an exchange station) connected to each radio terminal so that the radio terminals can interchange information from each other, and a data processing unit connected to the relay apparatus, each radio terminal having a circuit for inputting and outputting a voice signal and a circuit for inputting and outputting data whereby it can communicate with another radio terminals or with the data processing unit through the relay apparatus. The radio terminal of this invention further has a clock, and a circuit for storing a schedule inputted by the user thereby to automatically select a receiving mode such as a ringing mode or a nonringing mode in accordance with the contents of the schedule, the present time and so on.
    Type: Grant
    Filed: May 21, 1990
    Date of Patent: July 7, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Nobuo Tsukamoto, Hiroshi Kuwahara, Yuji Sakamoto, Kumiko Takikawa