Abstract: A process for fabricating a circuit board that includes a dielectric layer, a circuit layer, and an insulation layer. The circuit layer is disposed on the dielectric layer and has a pad region and a trace region. The insulation layer is disposed on the circuit layer and covers the trace region. Here, a thickness of the pad region is less than a thickness of the trace region.

Abstract: A circuit board includes a dielectric layer, a circuit layer, and an insulation layer. The circuit layer is disposed on the dielectric layer and has a pad region and a trace region. The insulation layer is disposed on the circuit layer and covers the trace region. Here, a thickness of the pad region is less than a thickness of the trace region.

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: A high frequency substrate includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a high-frequency signal transmission line. The first dielectric layer is formed on the first metal layer, and the second metal layer is formed on the first dielectric layer. The first and second metal layers are maintained in a stable voltage status due to the high dielectric coefficient of the first dielectric layer. Besides, the second dielectric layer is formed on the second metal layer. High speed and high frequency transmission are achieved when signals transmitting in the high-frequency transmission line formed on the second dielectric layer due to the low dielectric coefficient of the second dielectric layer.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: A high frequency substrate includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a high-frequency signal transmission line. The first dielectric layer is formed on the first metal layer, and the second metal layer is formed on the first dielectric layer. The first and second metal layers are maintained in stable voltage status due to the high dielectric coefficient of the first dielectric layer. Besides, the second dielectric layer is formed on the second metal layer. High speed and high frequency transmission are achieved when signals transmitting in the high-frequency transmission line formed on the second dielectric layer due to the low dielectric coefficient of the second dielectric layer.

Abstract: A high frequency substrate comprises at least a metal layer, a dielectric layer and a high frequency signal transmission line is provided. Of which, the dielectric layer, which is formed on the metal layer, has a dense structure and a number of closed voids with a filling material stuffed therein. Since the dielectric constant of a material is smaller than that of the dense structure, the overall dielectric constant of the dielectric layer is smaller than that of the dense structure. When the high frequency signal transmission line is deposited on the dielectric layer, the signal transmission speed in the high frequency signal transmission line will be improved, the energy loss of signals will be attenuated and so will signal transmission quality be maintained.

Abstract: A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.

Abstract: A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Abstract: A flip chip package substrate is disclosed. The substrate is correspondingly flip chip bonded to a first chip, a second chip, and so on, wherein these chips are of similar type of pad arrangement but of different pad pitches. The top face of the flip chip package substrate is provided with a plurality of bump pad groups, and these bump pad groups are respectively provided with a plurality of bump pads in the sequence of a first bump pad, a second bump pad, and so on, and a plurality of bump pads of the same bump pad group are electrically connected with each other, and the positions of the first bump pads are respectively corresponding to the positions of the second pads, and the rest may be inferred by analogy. Hence, these chips share the same flip chip package substrate.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Abstract: A flip chip package substrate is disclosed. The substrate is correspondingly flip chip bonded to a first chip, a second chip, and so on, wherein these chips are of similar type of pad arrangement but of different pad pitches. The top face of the flip chip package substrate is provided with a plurality of bump pad groups, and these bump pad groups are respectively provided with a plurality of bump pads in the sequence of a first bump pad, a second bump pad, and so on, and a plurality of bump pads of the same bump pad group are electrically connected with each other, and the positions of the first bump pads are respectively corresponding to the positions of the second pads, and the rest may be inferred by analogy. Hence, these chips share the same flip chip package substrate.

Abstract: A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Abstract: A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.

Abstract: A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Abstract: A substrate strip includes a plurality of substrate units wherein each of the substrate units is accepted for packaging a semiconductor package. The substrate strip comprises: a frame having at least one opening; at least one first substrate unit integrally formed with the strip frame; and at least one second substrate unit disposed in the opening and securely attached to the strip frame by an adhesive. The present invention further provides a method for making the substrate strip. The method is conducted by separating defected substrate units from a substrate strip and securely attaching accepted substrate units back to the substrate strip.