Patents by Inventor Kun-Ei Chen
Kun-Ei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369386Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Hsueh-Han LU, Kun-Ei CHEN, Chen-Chieh CHIANG, Ling-Sung WANG, Jun-Nan NIAN
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Publication number: 20230352351Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first conductive pad, a second conductive pad, a conductive material and a conductive coil. The first and second conductive pads are disposed over and electrically connected to the interconnection structure individually. The conductive material is electrically isolated from the interconnection structure, wherein bottom surfaces of the conductive material, the first conductive pad and the second conductive pad are substantially aligned. The conductive coil is disposed in the interconnection structure and overlapped by the conductive material. A manufacturing method of a semiconductor structure is also provided.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Inventors: PEI-LUM MA, KUN DA JHONG, HSUEH-HAN LU, KUN-EI CHEN, CHEN-CHIEH CHIANG, LING-SUNG WANG
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Publication number: 20230335390Abstract: A method for manufacturing a semiconductor structure is provided. The method may include several operations. A first layer is formed over a first region and a second region of a substrate. A first etching is performed on the first layer, thereby forming a first trench in the first region and a second trench in the second region. A first amorphization is performed on the first layer in the second region. A second etching is performed on the first layer, wherein an etching rate of the second etching in the second region is greater than an etching rate of the second etching in the first region.Type: ApplicationFiled: April 19, 2022Publication date: October 19, 2023Inventors: CHING KANG CHEN, KUN-EI CHEN, CHEN-CHIEH CHIANG, LING-SUNG WANG
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Publication number: 20230299179Abstract: A semiconductor structure and a method are provided. The method includes patterning a substrate to form a first fin structure in a first region and a second fin structure in a second region, wherein a first width of the first fin structure is greater than a second width of the second fin structure; forming a protecting layer on the second fin structure; and forming a first oxide layer over the first fin structure and forming a second oxide layer over the protecting layer, wherein a width of the first oxide layer is greater than a width of the second oxide layer.Type: ApplicationFiled: March 17, 2022Publication date: September 21, 2023Inventors: HSUEH-HAN LU, KUN-EI CHEN, CHEN-CHIEH CHIANG, LING-SUNG WANG
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Publication number: 20230135392Abstract: The present disclosure describes a semiconductor device having an isolation structure with a protection layer. The semiconductor device includes a substrate, a transistor with a source/drain (S/D) structure on the substrate, and an isolation structure on the substrate and adjacent to the transistor. The isolation structure includes a dielectric structure on the substrate, a protection layer on the dielectric structure, and a gate structure on the protection layer. The protection layer is disposed between the gate structure and the S/D structure.Type: ApplicationFiled: February 18, 2022Publication date: May 4, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-I CHENG, Chen-Chieh CHIANG, Kun-Ei CHEN, Pei-Lum MA
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Patent number: 11004973Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: GrantFiled: June 3, 2019Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
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Publication number: 20190288110Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Inventors: Chung-Ren SUN, Shiu-Ko JANGJIAN, Kun-Ei CHEN, Chun-Che LIN
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Patent number: 10312366Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: GrantFiled: July 28, 2017Date of Patent: June 4, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
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Publication number: 20170345928Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: ApplicationFiled: July 28, 2017Publication date: November 30, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ren SUN, Shiu-Ko JANGJIAN, Kun-Ei CHEN, Chun-Che LIN
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Patent number: 9722076Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: GrantFiled: August 29, 2015Date of Patent: August 1, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURNING CO., LTD.Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
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Publication number: 20170062612Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: ApplicationFiled: August 29, 2015Publication date: March 2, 2017Inventors: Chung-Ren SUN, Shiu-Ko JANGJIAN, Kun-Ei CHEN, Chun-Che LIN
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Patent number: 8900886Abstract: A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.Type: GrantFiled: June 1, 2012Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-Ei Chen, Jen-Yi Chen, Yi-Chung Lin, Chen-Chieh Chiang, Ling-Sung Wang
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Patent number: 8698217Abstract: A device includes a semiconductor substrate having a front side and a backside. An active image sensor pixel array is disposed on the front side of the semiconductor substrate. A metal shield is disposed on the backside of, and overlying, the semiconductor substrate. The metal shield has an edge facing the active image sensor pixel array. The metal shield has a middle width, and a top width greater than the middle width.Type: GrantFiled: March 23, 2012Date of Patent: April 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Hsu, Kun-Ei Chen, Huai-Tei Yang, Chien-Chung Chen
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Publication number: 20130323859Abstract: A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kun-Ei CHEN, Jen-Yi CHEN, Yi-Chung LIN, Chen-Chieh CHIANG, Ling-Sung WANG
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Patent number: 8586486Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.Type: GrantFiled: December 16, 2011Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Yi Chen, Kun-Ei Chen, Ling-Sung Wang, Chen-Chieh Chiang
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Metal Shield Structures in Backside Illumination Image Sensor Chips and Methods for Forming the Same
Publication number: 20130249039Abstract: A device includes a semiconductor substrate having a front side and a backside. An active image sensor pixel array is disposed on the front side of the semiconductor substrate. A metal shield is disposed on the backside of, and overlying, the semiconductor substrate. The metal shield has an edge facing the active image sensor pixel array. The metal shield has a middle width, and a top width greater than the middle width.Type: ApplicationFiled: March 23, 2012Publication date: September 26, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Hsu, Kun-Ei Chen, Huai-Tei Yang, Chien-Chung Chen -
Publication number: 20130157467Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jen-Yi CHEN, Kun-Ei CHEN, Ling-Sung WANG, Chen-Chieh CHANG
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Patent number: 8034722Abstract: A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.Type: GrantFiled: April 7, 2006Date of Patent: October 11, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Han Lin, Kun-Ei Chen
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Publication number: 20070238306Abstract: A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.Type: ApplicationFiled: April 7, 2006Publication date: October 11, 2007Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Han Lin, Kun-Ei Chen
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Patent number: 6965432Abstract: An apparatus and method for detecting mispositioned wafers attributable to transfer shift of the wafer are disclosed. A calibration wafer has a target region comprising a pattern of optically distinguishable features from which is determined the position of the calibration wafer within the chamber subsequent to its transfer therein. Preferably, the features comprise a pattern of colors that can be detected by spectroscopy. A preferred form and manner of providing such color features is by way of dielectric thin film filters.Type: GrantFiled: June 7, 2002Date of Patent: November 15, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Yi Wu, Kun-Ei Chen, San-Ching Lin