Patents by Inventor Kun-Ei Chen

Kun-Ei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130323859
    Abstract: A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Ei CHEN, Jen-Yi CHEN, Yi-Chung LIN, Chen-Chieh CHIANG, Ling-Sung WANG
  • Patent number: 8586486
    Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Yi Chen, Kun-Ei Chen, Ling-Sung Wang, Chen-Chieh Chiang
  • Publication number: 20130249039
    Abstract: A device includes a semiconductor substrate having a front side and a backside. An active image sensor pixel array is disposed on the front side of the semiconductor substrate. A metal shield is disposed on the backside of, and overlying, the semiconductor substrate. The metal shield has an edge facing the active image sensor pixel array. The metal shield has a middle width, and a top width greater than the middle width.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Hsu, Kun-Ei Chen, Huai-Tei Yang, Chien-Chung Chen
  • Publication number: 20130157467
    Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Yi CHEN, Kun-Ei CHEN, Ling-Sung WANG, Chen-Chieh CHANG
  • Patent number: 8034722
    Abstract: A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: October 11, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Han Lin, Kun-Ei Chen
  • Publication number: 20070238306
    Abstract: A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 11, 2007
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Han Lin, Kun-Ei Chen
  • Patent number: 6965432
    Abstract: An apparatus and method for detecting mispositioned wafers attributable to transfer shift of the wafer are disclosed. A calibration wafer has a target region comprising a pattern of optically distinguishable features from which is determined the position of the calibration wafer within the chamber subsequent to its transfer therein. Preferably, the features comprise a pattern of colors that can be detected by spectroscopy. A preferred form and manner of providing such color features is by way of dielectric thin film filters.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: November 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Yi Wu, Kun-Ei Chen, San-Ching Lin
  • Publication number: 20030227624
    Abstract: An apparatus and method for detecting mispositioned wafers attributable to transfer shift of the wafer are disclosed. A calibration wafer has a target region comprising a pattern of optically distinguishable features from which is determined the position of the calibration wafer within the chamber subsequent to its transfer therein. Preferably, the features comprise a pattern of colors that can be detected by spectroscopy. A preferred form and manner of providing such color features is by way of dielectric thin film filters.
    Type: Application
    Filed: June 7, 2002
    Publication date: December 11, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Yi Wu, Kun-Ei Chen, San-Ching Lin