Abstract: A friction sheet includes a fabric sheet with a friction surface formed on a surface of the fabric sheet and the friction sheet is attached to an outsole so as to provide the outsole better friction and grasp ability. The friction sheets are especially designed to be cooperated with thin outsoles.

Abstract: A material for making a shoe sole includes PVC (polyvinyl chloride) 100 parts by weight, DINP (plasticizer) 45-90 parts by weight, swelling powder 1-5 parts by weight, stabilizator 1-1.5 parts by weight, and foaming powder 0.5-4 parts by weight.

Abstract: A DDR and QDR converter and an interface, a motherboard and a memory module interface using the same. The DDR and QDR converter has a QDR interface, a DDR interface and a conversion core. The QDR interface is used to exchange a signal with QDR devices. The DDR interface is used to exchange a signal with DDR devices. The conversion core is used to convert QDR command and data formats into DDR command and data formats, and to convert DDR command and data formats into QDR command and data formats.

Abstract: Address converter apparatus and method to support various memory chips and an application system thereof. A flexibly programmed memory addressing circuit is used as a bridge between a control chip and a memory chip. A correct addressing method is selected according to a selected configuration value, so that the application system is not only able to use the control chip to support the memory chip, but is also able to use a new type of memory chip with multiple capacities. An optimal method is selected to partition or isolate the malfunctioning portion of the partly malfunctioning memory chip for further combination or simulation.

Abstract: A memory fault detection and isolation system method is proposed, which is designed for use on a memory device to isolate any faulted part of the memory device from being accessible. The proposed memory fault detection and isolation system method is characterized by the use of a decoding unit coupled between the access-control unit and the memory device to perform a row-address inversion mode to invert the row address of a faulted part of the memory device to the bottom half portion of the current memory scan range. Subsequently, the memory scan range is reduced to the bottom half portion to repeat a new memory scan until the remaining memory range reaches the minimum isolatable range so that the faulted part can be isolated from being accessible. This allows the memory device to be nevertheless usable in the event of the occurrence of a faulted part for effective use of the memory device.

Abstract: A memory command converter and its application system. The memory command converter serves as a command translator between an extended data output dynamic random access memory (EDO DRAM) and a synchronous dynamic random access memory (SDRAM) so that an application system for using EDO DRAM may also use mainstream SDRAM through the converter.

Abstract: A memory command converter and its application system. The memory command converter serves as a command translator between an extended data output dynamic random access memory (EDO DRAM) and a synchronous dynamic random access memory (SDRAM) so that an application system for using EDO DRAM may also use mainstream SDRAM through the converter.

Abstract: Address converter apparatus and method to support various memory chips and an application system thereof. A flexibly programmed memory addressing circuit is used as a bridge between a control chip and a memory chip. A correct addressing method is selected according to a selected configuration value, so that the application system is not only able to use the control chip to support the memory chip, but is also able to use a new type of memory chip with multiple capacities. An optimal method is selected to partition or isolate the malfunctioning portion of the partly malfunctioning memory chip for further combination or simulation. The system performance is enhanced, and the endurance of the system is improved.

Abstract: An SDR and DDR conversion device and associated interface cards, motherboards and memory module interfaces. The SDR and DDR conversion device includes a DDR interface device, an SDR interface device and a core conversion device. The DDR interface device exchanges signals with the DDR device while the SDR interface device exchanges signals with the SDR device. The core conversion device converts DDR instructions and data into SDR instructions and data and vice versa.

Abstract: A DDR and QDR converter and an interface, a motherboard and a memory module interface using the same. The DDR and QDR converter has a QDR interface, a DDR interface and a conversion core. The QDR interface is used to exchange a signal with QDR devices. The DDR interface is used to exchange a signal with DDR devices. The conversion core is used to convert QDR command and data formats into DDR command and data formats, and to convert DDR command and data formats into QDR command and data formats.

Abstract: A memory accelerator and associated interface card and motherboard. The memory accelerator has a memory bus acceleration system device and a memory bus accelerator. The memory bus acceleration system device processes signals between a chipset and the memory bus accelerator. The memory bus accelerator receives signals from the memory bus acceleration system device to conduct data transmission and reception and perform data conversion with corresponding memory. The method of increasing memory access speed includes providing an access command within an access cycle so that the memory bus accelerators can sequentially access data within the access cycle according to the access command and perform a data access operation with corresponding memory.

Abstract: A P.V.C. shoe sole includes a foam tissue defining a plurality of apertures. The shoe sole has a top face defining a plurality of cavities. Each of the cavities has a periphery formed with a compact tissue, thereby decreasing the weight of the entire unit volume of the shoe sole, and thereby providing a better support for the shoe sole.

Abstract: A T.P.R. shoe sole includes a foam tissue defining a plurality of apertures. The shoe sole has a top face defining a plurality of cavities. Each of the cavities has a periphery formed with a compact tissue, thereby decreasing the weight of the entire unit volume of the shoe sole, and thereby providing a better support for the shoe sole.

Abstract: An SDR and DDR conversion device and associated interface cards, motherboards and memory module interfaces. The SDR and DDR conversion device includes a DDR interface device, an SDR interface device and a core conversion device. The DDR interface device exchanges signals with the DDR device while the SDR interface device exchanges signals with the SDR device. The core conversion device converts DDR instructions and data into SDR instructions and data and vice versa.

Abstract: A SDR and QDR converter and an interface, a motherboard and a memory module interface using the same. The converter of SDR and QDR has a QDR interface, a SDR interface and a conversion core. The QDR interface is used to exchange a signal with QDR devices. The SDR interface is used to exchange a signal with SDR devices. The conversion core is used to convert QDR command and data formats into SDR command and data formats, and to convert SDR command and data formats into QDR command and data formats.