Patents by Inventor Kun-Hsien Lee
Kun-Hsien Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240220055Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.Type: ApplicationFiled: March 19, 2024Publication date: July 4, 2024Inventors: Chen-Cheng LIN, Chia-I LIU, Kun-Hsien LEE, Hung-Wei TSENG
-
Publication number: 20240224394Abstract: A display module includes a front light module and a reflective display panel. The front light module comprises a light source and a light guide plate. The light source comprises a plurality of major light sources comprising a first color temperature and a plurality of auxiliary light sources comprising a second color temperature. The first color temperature is different from the second color temperature. The light guide plate comprises a front surface comprising a light mixing area and an active area. The light mixing area comprises a light entrance surface. The light source is disposed adjacent to the light entrance surface. The reflective display panel is disposed on a back surface of the light guide plate. The light mixing area of the light guide plate is foldable. When the light mixing area is folded, the light mixing area is on the back surface of the light guide plate.Type: ApplicationFiled: September 24, 2023Publication date: July 4, 2024Inventors: Kun-Hsien LEE, Ching-Huan LIAO, Hsin-Tao HUANG
-
Publication number: 20240184036Abstract: A display device including a display panel and a light source module is provided. The light source module includes a flexible light guide and a light emitting element. The flexible light guide has a light exiting portion and a light incident portion. The flexible light guide is bent so that the display panel is located between the light exiting portion and the light incident portion. The light incident portion has a light incident surface at a terminal. A thickness of the light incident portion is gradually increased toward the light incident surface. The light emitting element is disposed to face toward the light incident surface.Type: ApplicationFiled: November 10, 2023Publication date: June 6, 2024Applicant: E Ink Holdings Inc.Inventors: Kun-Hsien Lee, Ching-Huan Liao
-
Patent number: 11966546Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.Type: GrantFiled: August 19, 2021Date of Patent: April 23, 2024Assignee: E Ink Holdings Inc.Inventors: Chen-Cheng Lin, Chia-I Liu, Kun-Hsien Lee, Hung-Wei Tseng
-
Publication number: 20240120419Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.Type: ApplicationFiled: December 5, 2023Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chun Chou, Yu-Hung Chang, Kun-Hsien Lee
-
Publication number: 20240105839Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chun Chou, Yu-Hung Chang, Kun-Hsien Lee
-
Patent number: 11881527Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.Type: GrantFiled: September 12, 2021Date of Patent: January 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chun Chou, Yu-Hung Chang, Kun-Hsien Lee
-
Patent number: 11789316Abstract: A front light module includes a foldable light guide plate, a light source, an upper insulating layer, an upper optical adhesive layer, a lower insulating layer, and a lower optical adhesive layer. The top surface and the bottom surface of the foldable light guide plate adjoin the light incident surface of the foldable light guide plate. The light source faces toward the light incident surface. The upper insulating layer is located on the top surface. The upper optical adhesive layer is located on the upper insulating layer, and a storage modulus of the upper optical adhesive layer is less than a storage modulus of the upper insulating layer. The lower optical adhesive layer is located on a bottom surface of the lower insulating layer, and a storage modulus of the lower optical adhesive layer is less than a storage modulus of the lower insulating layer.Type: GrantFiled: December 7, 2022Date of Patent: October 17, 2023Assignee: E Ink Holdings Inc.Inventors: Kun-Hsien Lee, Sheng-Chieh Tai, Yi-Yu Tsai, Hsin-Tao Huang
-
Publication number: 20230253497Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chun Chou, Te-Chi Yen, Yu-Hung Chang, Kun-Hsien Lee, Kai-Lin Lee
-
Publication number: 20230229041Abstract: A front light module includes a foldable light guide plate, a light source, an upper insulating layer, an upper optical adhesive layer, a lower insulating layer, and a lower optical adhesive layer. The top surface and the bottom surface of the foldable light guide plate adjoin the light incident surface of the foldable light guide plate. The light source faces toward the light incident surface. The upper insulating layer is located on the top surface. The upper optical adhesive layer is located on the upper insulating layer, and a storage modulus of the upper optical adhesive layer is less than a storage modulus of the upper insulating layer. The lower optical adhesive layer is located on a bottom surface of the lower insulating layer, and a storage modulus of the lower optical adhesive layer is less than a storage modulus of the lower insulating layer.Type: ApplicationFiled: December 7, 2022Publication date: July 20, 2023Inventors: Kun-Hsien LEE, Sheng-Chieh TAI, Yi-Yu TSAI, Hsin-Tao HUANG
-
Patent number: 11664450Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.Type: GrantFiled: March 29, 2021Date of Patent: May 30, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chun Chou, Te-Chi Yen, Yu-Hung Chang, Kun-Hsien Lee, Kai-Lin Lee
-
Publication number: 20230052714Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.Type: ApplicationFiled: September 12, 2021Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chun Chou, Yu-Hung Chang, Kun-Hsien Lee
-
Patent number: 11488870Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.Type: GrantFiled: April 8, 2020Date of Patent: November 1, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tien-Yu Hsieh, Kuan-Ti Wang, Han-Chen Chen, Kun-Hsien Lee
-
Publication number: 20220302118Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.Type: ApplicationFiled: April 14, 2021Publication date: September 22, 2022Inventors: Kuo-Hsing Lee, Kun-Hsien Lee, Sheng-Yuan Hsueh, Chang-Chien Wong, Ching-Hsiang Tseng, Tsung-Hsun Wu, Chi-Horn Pai, Shih-Chieh Hsu
-
Patent number: 11450670Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.Type: GrantFiled: April 14, 2021Date of Patent: September 20, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Kun-Hsien Lee, Sheng-Yuan Hsueh, Chang-Chien Wong, Ching-Hsiang Tseng, Tsung-Hsun Wu, Chi-Horn Pai, Shih-Chieh Hsu
-
Publication number: 20220271161Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.Type: ApplicationFiled: March 29, 2021Publication date: August 25, 2022Inventors: Ling-Chun Chou, Te-Chi Yen, Yu-Hung Chang, Kun-Hsien Lee, Kai-Lin Lee
-
Patent number: 11322215Abstract: A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.Type: GrantFiled: May 21, 2021Date of Patent: May 3, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pin Tsao, Tsung-Hsun Wu, Liang-Wei Chiu, Kuo-Hsing Lee, Sheng-Yuan Hsueh, Kun-Hsien Lee, Chang-Chien Wong
-
Publication number: 20220129093Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.Type: ApplicationFiled: August 19, 2021Publication date: April 28, 2022Inventors: Chen-Cheng LIN, Chia-I LIU, Kun-Hsien LEE, Hung-Wei TSENG
-
Patent number: 11300271Abstract: The invention provides a light source module including a light guide plate and light emitting elements. The light guide plate includes a main plate body and a plurality of optical microstructures. The main plate body has a light emitting surface and a back surface opposite to each other, and a light incident surface connected therebetween. The optical microstructures are formed on the back surface. Each optical microstructure includes at least two sections connected to each other, each section having a reflective surface. The light emitting elements are disposed on the light incident surface, and light emitted by each of the light emitting elements is reflected by at least some of the reflective surfaces and transmitted to the light emitting surface. In any optical microstructure, the reflective surfaces are not parallel to each other.Type: GrantFiled: September 10, 2020Date of Patent: April 12, 2022Assignee: CHAMP VISION DISPLAY INC.Inventors: Hsin-Hung Lee, Chin-Ku Liu, Chung-Hao Wu, Kun-Hsien Lee
-
Publication number: 20210287942Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.Type: ApplicationFiled: April 8, 2020Publication date: September 16, 2021Inventors: Tien-Yu Hsieh, Kuan-Ti Wang, Han-Chen Chen, Kun-Hsien Lee