Patents by Inventor Kun-Ju Li

Kun-Ju Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225932
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20210151666
    Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 11004897
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Grant
    Filed: August 4, 2019
    Date of Patent: May 11, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Publication number: 20210119115
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: December 27, 2020
    Publication date: April 22, 2021
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Patent number: 10916694
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20210005662
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
    Type: Application
    Filed: August 4, 2019
    Publication date: January 7, 2021
    Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
  • Patent number: 10804461
    Abstract: A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench. Subsequently, a nitrogen plasma step (N2 plasma) is performed on the dielectric layer, a cleaning step is performed to remove the residue in the alignment mark trench, and a patterned magnetic tunneling junction, MTJ) film is laminated on the contact window.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 13, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Jung Liu, Kun-Ju Li, Ang Chan, Chau-Chung Hou, Yu-Lung Shih
  • Patent number: 10722998
    Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Kun-Ju Li, Po-Cheng Huang, Chun-Liang Liu
  • Publication number: 20200212290
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 2, 2020
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20200185597
    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Kun-Ju Li, Hsin-Jung Liu, I-Ming Tseng, Chau-Chung Hou, Yu-Lung Shih, Fu-Chun Hsiao, Hui-Lin Wang, Tzu-Hsiang Hung, Chih-Yueh Li, Ang Chan, Jing-Yin Jhang
  • Patent number: 10535817
    Abstract: A method of manufacturing an embedded magnetoresistive random access memory including the following steps is provided. A memory cell stack structure is formed on a substrate structure. The memory cell stack structure includes a first electrode, a second electrode, and a magnetic tunnel junction structure. A first dielectric layer covering the memory cell stack structure is formed. A metal nitride layer is formed on the first dielectric layer. A second dielectric layer is formed on the metal nitride layer. A first CMP process is performed on the second dielectric layer to expose the metal nitride layer by using the metal nitride layer as a stop layer. An etch back process is performed to completely remove the metal nitride layer and expose the first dielectric layer. A second CMP process is performed to expose the second electrode. The manufacturing method can have a better planarization effect.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: January 14, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Kun-Ju Li
  • Patent number: 10446745
    Abstract: A method of manufacturing a magnetoresistive random access memory cell includes the following steps. A first dielectric layer including a first metal line therein is formed on a substrate. A patterned second dielectric layer is formed over the first dielectric layer, wherein the patterned second dielectric layer includes a recess exposing the first metal line. A barrier layer conformally covers the recess and the patterned second dielectric layer. A metal fills up the recess and on the barrier layer. The metal is planarized until the barrier layer being exposed by serving the barrier layer as a stop layer. A magnetic tunneling junction and a top electrode over the metal are formed, thereby a magnetoresistive random access memory cell being formed.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Kun-Ju Li
  • Patent number: 10290723
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Publication number: 20190070706
    Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 7, 2019
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Kun-Ju Li, Po-Cheng Huang, Chun-Liang Liu
  • Patent number: 10192826
    Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu
  • Patent number: 10103034
    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
  • Publication number: 20180269308
    Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Patent number: 10049887
    Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 14, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chieh Hsu, Fu-Shou Tsai, Yu-Ting Li, Yi-Liang Liu, Kun-Ju Li
  • Patent number: 10008581
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Tsen Lu, Chien-Ming Lai, Lu-Sheng Chou, Ya-Huei Tsai, Ching-Hsiang Chiu, Yu-Tung Hsiao, Chen-Ming Huang, Kun-Ju Li, Yu-Ping Wang
  • Publication number: 20180138125
    Abstract: A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 17, 2018
    Inventors: Kun-Ju Li, Kuo-Chin Hung, Min-Chuan Tsai, Wei-Chuan Tsai, Yi-Han Liao, Chun-Tsen Lu, Fu-Shou Tsai, Li-Chieh Hsu