Abstract: A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

Abstract: A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A plurality of fin structures are formed in a first area and a second area of a substrate. A first density of the fin structures in the first area is lower than a second density of the fin structures in the second area. A gate dielectric layer is formed on the fin structures. An amorphous silicon layer is formed on the gate dielectric layer and the fin structures in the first area and the second area. Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser. The crystalline silicon layer disposed in the first area and the amorphous silicon layer disposed in the second area are polished.

Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract: A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract: A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer.

Abstract: A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer.

Abstract: A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.