Abstract: A PLL circuit generates an output signal having an output frequency and includes a voltage-to-current conversion circuit, a frequency compensation circuit, and an ICO. The voltage-to-current conversion circuit is configured to generate a first control current according to a control voltage, wherein the control voltage is generated according to a reference signal and a feedback signal derived from the output signal. The frequency compensation circuit is configured to generate a second control current according to the control voltage. The ICO generates the output signal according to an oscillation current, wherein the oscillation current is a sum of the first control current and the second control current. In response to the frequency compensation circuit detecting that the control voltage is out of a predetermined range, the second control current is controlled to be negatively correlated with the output frequency.

Abstract: A PLL circuit generates an output signal having an output frequency and includes a voltage-to-current conversion circuit, a frequency compensation circuit, and an ICO. The voltage-to-current conversion circuit is configured to generate a first control current according to a control voltage, wherein the control voltage is generated according to a reference signal and a feedback signal derived from the output signal. The frequency compensation circuit is configured to generate a second control current according to the control voltage. The ICO generates the output signal according to an oscillation current, wherein the oscillation current is a sum of the first control current and the second control current. In response to the frequency compensation circuit detecting that the control voltage is out of a predetermined range, the second control current is controlled to be negatively correlated with the output frequency.

Abstract: A device for correcting a duty cycle, comprising: a duty adjustor circuit, configured to receive an input clock signal and a tuning signal, to generate an output clock signal; a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage; a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage; a first sampling and hold circuit, configured to sample the first voltage to generate a first sampled voltage; a second sampling and hold circuit, configured to sample the second voltage to generate a second sampled voltage; and an error amplifier, configured to generate the tuning signal according to a difference value between the first sampled voltage and the second sampled voltage.

Abstract: A device for correcting a duty cycle, comprising: a duty adjustor circuit, configured to receive an input clock signal and a tuning signal, to generate an output clock signal; a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage; a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage; a first sampling and hold circuit, configured to sample the first voltage to generate a first sampled voltage; a second sampling and hold circuit, configured to sample the second voltage to generate a second sampled voltage; and an error amplifier, configured to generate the tuning signal according to a difference value between the first sampled voltage and the second sampled voltage.

Abstract: An impedance matching circuit and an interface circuit are provided. The impedance matching circuit includes a reference-voltage generation circuit, a control-signal generation circuit, and a circuit subunit. The reference-voltage generation circuit generates a reference voltage. The control-signal generation circuit generates a plurality of control signals. The circuit subunit is coupled to the reference-voltage generation circuit and the control-signal generation circuit. The circuit subunit receives the reference voltage and the control signals. The circuit subunit includes a plurality of transistors. The plurality of transistors are turned on or off according to levels of the control signals, and the plurality of transistors provide an impedance which matches the impedance of a receiver when the interface circuit is powered. The reference voltage is provided to bulks of the transistors, so that the voltages of the bulks of the transistors are not equal to zero volts.

Abstract: A current-mode logic circuit is provided. The current-mode logic circuit includes a transmitter module. The transmitter module includes an output impedance circuit, a switch circuit, and a current source. The output impedance circuit provides an adjustable output resistor. The adjustable output resistor includes floating resistors and/or pull-up resistors. The switch circuit is coupled to the output impedance circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls high-low level switching of the differential input signals and the differential output signals according to the adjustable output resistor. The current source is coupled to the output impedance circuit and the switch circuit. The current source provides currents to the output impedance circuit and the switch circuit.

Abstract: An impedance matching circuit and an interface circuit are provided. The impedance matching circuit includes a reference-voltage generation circuit, a control-signal generation circuit, and a circuit subunit. The reference-voltage generation circuit generates a reference voltage. The control-signal generation circuit generates a plurality of control signals. The circuit subunit is coupled to the reference-voltage generation circuit and the control-signal generation circuit. The circuit subunit receives the reference voltage and the control signals. The circuit subunit includes a plurality of transistors. The plurality of transistors are turned on or off according to levels of the control signals, and the plurality of transistors provide an impedance which matches the impedance of a receiver when the interface circuit is powered. The reference voltage is provided to bulks of the transistors, so that the voltages of the bulks of the transistors are not equal to zero volts.

Abstract: A current-mode logic circuit is provided. The current-mode logic circuit includes a transmitter module. The transmitter module includes an output impedance circuit, a switch circuit, and a current source. The output impedance circuit provides an adjustable output resistor. The adjustable output resistor includes floating resistors and/or pull-up resistors. The switch circuit is coupled to the output impedance circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls high-low level switching of the differential input signals and the differential output signals according to the adjustable output resistor. The current source is coupled to the output impedance circuit and the switch circuit. The current source provides currents to the output impedance circuit and the switch circuit.

Abstract: A pre-driver circuit is provided. The pre-driver circuit includes a switch circuit, a common-mode voltage control circuit, and a current supply circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls switching between a high level and a low level of the differential output signals and the differential input signals. The common-mode voltage control circuit is coupled to the switch circuit. The common-mode voltage control circuit receives a reference voltage and controls a common-mode voltage of the differential output signals according to the reference voltage. The current supply circuit is coupled to the switch circuit and the common-mode voltage control circuit. The current supply circuit provides a driving current for the switch circuit and the common-mode voltage control circuit.

Abstract: A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter.

Abstract: An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal.

Abstract: A voltage regulator includes a pass transistor, an operational amplifier and a voltage divider circuit. The pass transistor receives a supply voltage to generate a regulated output voltage according to a control signal. The operational amplifier generates the control signal according to a feedback voltage. The voltage divider circuit generates the feedback voltage at a feedback node according to the regulated output voltage, and includes a string of resistors and a stabilization element. The string of resistors is coupled to the pass transistor and includes multiple resistors. The stabilization element is coupled to the resistors and receives the regulated output voltage.

Abstract: A method for configuring a plurality of analog-to-digital converter (ADC) keys includes: utilizing a processor for determining a plurality of divided-voltages respectively corresponding to the Keys according to a plurality of voltage variation ranges respectively corresponding to the Keys; and calculating a plurality of resistive values of a voltage dividing model according to at least the divided-voltages, wherein the voltage dividing model has a plurality of voltage dividing configurations respectively corresponding to the keys.

Abstract: A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter.

Abstract: An Analog to Digital Converter (ADC), an analog-to-digital conversion method, and an integrated circuit including the ADC. The ADC includes an input adjustment buffer stage, a sub-ADC, and a sample switch. The sample switch is coupled between the output node of the input adjustment buffer stage and the input node of the sub-ADC. When the sample switch is opened, the input adjustment buffer stage is configured to switch between a first work state and a second work state according to a predetermined rule, and to adjust an input voltage signal of the input adjustment buffer stage based on transitions between the first and second work states. When the sample switch is closed, the input adjustment buffer stage is configured to provide an adjusted voltage signal to the input node of the sub-ADC, and the sub-ADC is configured to perform an analog-to-digital conversion onto the adjusted voltage signal.

Abstract: A method for configuring a plurality of analog-to-digital converter (ADC) keys includes: utilizing a processor for determining a plurality of divided-voltages respectively corresponding to the Keys according to a plurality of voltage variation ranges respectively corresponding to the Keys; and calculating a plurality of resistive values of a voltage dividing model according to at least the divided-voltages, wherein the voltage dividing model has a plurality of voltage dividing configurations respectively corresponding to the keys.

Abstract: A voltage regulator includes a pass transistor, an operational amplifier and a voltage divider circuit. The pass transistor receives a supply voltage to generate a regulated output voltage according to a control signal. The operational amplifier generates the control signal according to a feedback voltage. The voltage divider circuit generates the feedback voltage at a feedback node according to the regulated output voltage, and includes a string of resistors and a stabilization element. The string of resistors is coupled to the pass transistor and includes multiple resistors. The stabilization element is coupled to the resistors and receives the regulated output voltage.

Abstract: An analog-to-digital converter is provided and comprises a most significant bit (MSB) conversion module, a successive approximation register analog-to-digital converter (SAR ADC) module, and an operation module. The MSB conversion module receives an analog signal to be converted, and converts the analog signal to an MSB with M bits, and obtains a redundancy signal. The SAR ADC module is coupled to the MSB conversion module. The SAR ADC receives the redundancy signal and processes the redundancy signal to be a least significant bit (LSB) with N bits. The operation module is coupled to the MSB conversion module and the SAR ADC module. The operation module receives the MSB with the M bits and the LSB with the N bits and generates a first digital signal with (M+N) bits. Each of M and N is positive, and (M+N) is a positive integer.