Abstract: A conductor trace structure reducing insertion loss of circuit board, the circuit board laminates an outer layer circuit board, an inner layer circuit board and a glass fiber resin films which arranged between each board; before laminated process, the conductor traces of the inner layers had formed by etching of imaging transfer process and conductor traces had been roughed process for making the glass fiber resin films having good adhesive performance during laminating; before etching of imaging transfer process that forms the conductor traces of the outer layers or solder resist coat process or coating polymer materials, the conductor traces have been roughed process to make insulating resin layer of the solder resist coat or polymer materials to has better associativity; wherein a smooth trench is formed by physical or chemical process constructed on the roughed conductor traces surface to guide electric ions transmitted on these smooth trench surface to enhance electric ions transmission rate, resulting i

Abstract: The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Abstract: An MRAM cell has a bottom electrode, a metal tunneling junction, and a top electrode. The metal tunneling junction has a side surface between the bottom electrode and the top electrode. A thin layer on the side surface includes one or more compounds of a metal found in one of the electrodes. The thin layer has a lower conductance than the MTJ. The electrode metal may have been deposited on the side during MTJ patterning and subsequently been reacted to form a compound having a lower conductance than a nitride of the electrode metal. The thin layer may include an oxide deposited over the redeposited electrode metal. The thin layer may include a compound of the electrode metal deposited over the redeposited electrode metal. A silicon nitride spacer may be formed over the thin layer without forming nitrides of the electrode metal.

Abstract: An exemplary method for forming spacer stacks with metallic compound layers is provided. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.

Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.

Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.

Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.

Abstract: The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes depositing a hard mask. A multi-layer structure is deposited over the hard mark. The multi-layer structure includes a bottom layer, a first middle layer over the bottom layer, a second middle layer over the first middle layer, and a top layer over the second middle layer. The first middle layer comprises a SiCxHyOz material in which the SiCxHyOz material has a silicon-to-silicon bond content in a range from about 0.5% to about 5%. The multi-layer structure is patterned to form a patterned first middle layer having openings. The hard mask is etched through the openings in the patterned first middle layer.

Abstract: The present disclosure describes an exemplary method that forms spacer stacks with metallic compound layers. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes depositing a hard mask. A multi-layer structure is deposited over the hard mark. The multi-layer structure includes a bottom layer, a first middle layer over the bottom layer, a second middle layer over the first middle layer, and a top layer over the second middle layer. The first middle layer comprises a SiCxHyOz material in which the SiCxHyOz material has a silicon-to-silicon bond content in a range from about 0.5% to about 5%. The multi-layer structure is patterned to form a patterned first middle layer having openings. The hard mask is etched through the openings in the patterned first middle layer.

Abstract: An impedance matching circuit and an interface circuit are provided. The impedance matching circuit includes a reference-voltage generation circuit, a control-signal generation circuit, and a circuit subunit. The reference-voltage generation circuit generates a reference voltage. The control-signal generation circuit generates a plurality of control signals. The circuit subunit is coupled to the reference-voltage generation circuit and the control-signal generation circuit. The circuit subunit receives the reference voltage and the control signals. The circuit subunit includes a plurality of transistors. The plurality of transistors are turned on or off according to levels of the control signals, and the plurality of transistors provide an impedance which matches the impedance of a receiver when the interface circuit is powered. The reference voltage is provided to bulks of the transistors, so that the voltages of the bulks of the transistors are not equal to zero volts.

Abstract: A current-mode logic circuit is provided. The current-mode logic circuit includes a transmitter module. The transmitter module includes an output impedance circuit, a switch circuit, and a current source. The output impedance circuit provides an adjustable output resistor. The adjustable output resistor includes floating resistors and/or pull-up resistors. The switch circuit is coupled to the output impedance circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls high-low level switching of the differential input signals and the differential output signals according to the adjustable output resistor. The current source is coupled to the output impedance circuit and the switch circuit. The current source provides currents to the output impedance circuit and the switch circuit.

Abstract: An impedance matching circuit and an interface circuit are provided. The impedance matching circuit includes a reference-voltage generation circuit, a control-signal generation circuit, and a circuit subunit. The reference-voltage generation circuit generates a reference voltage. The control-signal generation circuit generates a plurality of control signals. The circuit subunit is coupled to the reference-voltage generation circuit and the control-signal generation circuit. The circuit subunit receives the reference voltage and the control signals. The circuit subunit includes a plurality of transistors. The plurality of transistors are turned on or off according to levels of the control signals, and the plurality of transistors provide an impedance which matches the impedance of a receiver when the interface circuit is powered. The reference voltage is provided to bulks of the transistors, so that the voltages of the bulks of the transistors are not equal to zero volts.

Abstract: A current-mode logic circuit is provided. The current-mode logic circuit includes a transmitter module. The transmitter module includes an output impedance circuit, a switch circuit, and a current source. The output impedance circuit provides an adjustable output resistor. The adjustable output resistor includes floating resistors and/or pull-up resistors. The switch circuit is coupled to the output impedance circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls high-low level switching of the differential input signals and the differential output signals according to the adjustable output resistor. The current source is coupled to the output impedance circuit and the switch circuit. The current source provides currents to the output impedance circuit and the switch circuit.

Abstract: A pre-driver circuit is provided. The pre-driver circuit includes a switch circuit, a common-mode voltage control circuit, and a current supply circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls switching between a high level and a low level of the differential output signals and the differential input signals. The common-mode voltage control circuit is coupled to the switch circuit. The common-mode voltage control circuit receives a reference voltage and controls a common-mode voltage of the differential output signals according to the reference voltage. The current supply circuit is coupled to the switch circuit and the common-mode voltage control circuit. The current supply circuit provides a driving current for the switch circuit and the common-mode voltage control circuit.

Abstract: A power control system and a power control method are provided. The power control system is adapted to a computer device. The computer device comprises an embedded controller and a power supply both coupled to each other. The power supply provides power to the embedded controller. The power control system comprises a device switch input terminal and a logic output terminal. The device switch input terminal receives a trigger signal from a component of the computer device to change a state of the computer system. The logic output terminal is coupled to the power supply and performs on-off control of the power supply to provide or stop power to the embedded controller when the switch input terminal receives the trigger signal.

Abstract: An eyelash brush may include a brush rod disposed with a grip portion at one end, and a pivot-connecting end at the other end with a cambered end portion and two beveled guiding surfaces on both sides. A pivot hole is disposed at center of the two beveled guiding surfaces. Two position portions are disposed by two sides of the cambered end portion of the pivot-connecting end for positioning and pressing against. A movable rod is coupled with an eyelash brush at one end and two pivot portions are disposed at the other end, and two pivot rods are protrudingly disposed on opposite inner sides of the two pivot portions. A pivot groove corresponding to a thickness of the pivot-connecting end of the brush rod is formed between the two pivot portions so that the oppositely disposed pivot rods of two pivot portions can be pressed inside the pivot hole.

Abstract: A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter.