Abstract: An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.

Abstract: A via forming method is provided. The via forming method includes: forming via-holes in a substrate; putting the substrate having the via-holes in a first solution to fill the via-holes with the first solution; sinking the metal particles into the via-holes by supplying a second solution containing metal particles to the first solution, in which there is the substrate; and performing a first curing process of heat-treating the substrate having the via-holes filled with the metal particles so as to form vias in the via-holes. Further, a method of manufacturing a multi-chip package using the via forming method is provided.

Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.

Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.

Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes ar

Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.

Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible

Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.

Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible

Abstract: Capacitor and method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, the capacitor including a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact electrically, and the method including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a

Abstract: A method for fabricating a capacitor in a DRAM cell, includes the steps of: forming a plurality of wordlines each having a first cap insulating film on a semiconductor substrate; forming source/drain impurity regions in an active region of the semiconductor substrate on both sides of each of the wordlines; forming first sidewall insulating films at the both sides of said each of the wordlines; forming first plugs for contacting either capacitor nodes or bitlines on each of the source/drain impurity regions; forming an interlayer insulating film on the semiconductor substrate and forming a contact hole to the first plugs for contacting to the bitlines therein; forming a plurality of bitlines in a direction perpendicular to the wordlines, each of the bitlines being in contact with the first plugs, and having a second cap insulating film; forming second sidewall insulating films at both sides of each of the bitlines and selectively removing the interlayer insulating film to expose surfaces of the first plugs; fo

Abstract: Capacitor and method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, the capacitor including a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact electrically, and the method including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a

Abstract: A method for fabricating a semiconductor memory, in which a resistive layer is formed of a material identical to a material of a cell plug layer at a time of formation of the cell plug layer.

Abstract: Capacitor and method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, the capacitor including a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact electrically, and the method including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a