Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE enters a first radio resource control (RRC) connection with a first base station of a first network. The UE receives, from the first base station, an indication that enables the UE to send a first request for deactivating or releasing resources used for communications with the first base station. In response to a determination to enter a second RRC connection with a second base station of a second network, the UE sends, to the first base station, the first request for deactivating or releasing the resources. The UE enters the second RRC connection with the second base station while maintaining the first RRC connection with the first base station.

Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

Abstract: Among other things, one or more techniques and/or systems are provided for cleaning a polishing module of a semiconductor polishing apparatus. Purge air flow can be supplied into the polishing module (e.g., directed towards a polishing unit, a shield, and/or other polishing components) to create turbulence air flow within the polishing module. An auxiliary exhaust can be invoked to exhaust one or more particulates removed from the polishing module by the turbulence air flow. A purge air flow cycle can be performed by cycling the purge air flow and the auxiliary exhaust between on and off states. One or more purge air flow cycles can be performed during a main air flow cycle where laminar air flow is supplied into the polishing module and exhausted using a main exhaust. In this way, one or more particulates can be cleaned from the polishing module.

Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

Abstract: A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.

Abstract: Among other things, one or more techniques and/or systems are provided for driving a body of a polishing head using an alignment gear. That is, an alignment gear, coupled to a housing of the polishing head, can transfer rotational force from the housing to the body responsive to the alignment gear being mated with a channel associated with the body. For example, the housing can supply pressure to the body, resulting in the body and the housing moving towards one another into a mated state. When the body and the housing are in the mated state, the alignment gear can mate with the channel (e.g., the alignment gear can fit within the channel). In this way, the alignment gear can drive the body by transferring rotational force to the body, resulting in the body rotating a semiconductor wafer against a polishing pad to polish the semiconductor wafer, for example.

Abstract: A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter.

Abstract: Among other things, one or more techniques and/or systems are provided for driving a body of a polishing head using an alignment gear. That is, an alignment gear, coupled to a housing of the polishing head, can transfer rotational force from the housing to the body responsive to the alignment gear being mated with a channel associated with the body. For example, the housing can supply pressure to the body, resulting in the body and the housing moving towards one another into a mated state. When the body and the housing are in the mated state, the alignment gear can mate with the channel (e.g., the alignment gear can fit within the channel). In this way, the alignment gear can drive the body by transferring rotational force to the body, resulting in the body rotating a semiconductor wafer against a polishing pad to polish the semiconductor wafer, for example.

Abstract: Among other things, one or more techniques and/or systems are provided for cleaning a polishing module of a semiconductor polishing apparatus. Purge air flow can be supplied into the polishing module (e.g., directed towards a polishing unit, a shield, and/or other polishing components) to create turbulence air flow within the polishing module. An auxiliary exhaust can be invoked to exhaust one or more particulates removed from the polishing module by the turbulence air flow. A purge air flow cycle can be performed by cycling the purge air flow and the auxiliary exhaust between on and off states. One or more purge air flow cycles can be performed during a main air flow cycle where laminar air flow is supplied into the polishing module and exhausted using a main exhaust. In this way, one or more particulates can be cleaned from the polishing module.

Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.

Abstract: An electric apparatus with ESD protection effect is provided. The electric apparatus comprises a high-side unit, a low-side unit, and a level shifter. The high-side unit comprises a first pad and a second pad. The low-side unit comprises a third pad and a fourth pad. The level shifter is connected between the first pad and the fourth pad. The level shifter comprises a first resistor, a clamp element, a second resistor, and an N-type transistor. The first resistor is connected between the first pad and a first node. The clamp element is connected between the first pad and a second node. The second resistor is connected between the first node and the second node. The N-type transistor has a source and a body connected to the fourth pad, a drain connected to the first node, and a gate connected to the low-side unit.

Abstract: A touch sensing device includes four driving electrodes, four sensing circuits, a controller and a substrate. Each sensing circuit is coupled to one of the four driving electrodes, for sensing electrical charges of the corresponding sensing electrode. The four driving electrodes, disposed on the substrate, are electrically independent to each other. Each sensing circuit detects the electrical charges of the corresponding driving electrode, and generates a count according to the electrical charges of the corresponding driving electrode. The controller calculates a position of a touch point on the touch sensing device according to counts generated by the four sensing circuits.

Abstract: The invention provides a testkey structure for testing a chip. The testkey structure includes a metal pad and a first groove, wherein the first groove is disposed on the metal pad. The first groove is located between a first signal lead and a second signal lead of the chip. According to the first groove, the first signal lead and the second signal lead could be separated from each other to prevent the first signal lead and the second signal lead from shorting.

Abstract: A semiconductor structure and a manufacture method thereof are disclosed. The semiconductor structure includes a semiconductor wafer having a plurality of semiconductor device dies, wherein each of the semiconductor device dies includes a die body, a metal wiring layer, a bump, and a metal layer. The metal wiring layer is formed on the die body while the bump is formed on the metal wiring layer during the semiconductor front-end-of-line (FEOL) process and protrudes from the die body. The metal layer is disposed on one side of the bump opposite to the metal wiring layer, wherein the activity of the metal layer is smaller than the activity of the bump. In this way, the semiconductor structure of the present invention is easy to be manufactured and the manufacture cost is also reduced.

Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.

Abstract: An integrated circuit with an electrostatic discharge protection circuit includes a first power pad, a second power pad, at least a circuit module, and a power clamp circuit. The circuit module includes a signal pad, an internal circuit and a first bipolar transistor. A first parasitical resistance is coupled between a collector of the first bipolar transistor and the second power pad. There is at least a metal-oxide semiconductor (MOS) transistor and at least a first parasitical bipolar transistor included within the power clamp circuit.

Abstract: An integrated circuit with an electrostatic discharge protection circuit includes a first power pad, a second power pad, at least a circuit module, and a power clamp circuit. The circuit module includes a signal pad, an internal circuit and a first bipolar transistor. A first parasitical resistance is coupled between a collector of the first bipolar transistor and the second power pad. There is at least a metal-oxide semiconductor (MOS) transistor and at least a first parasitical bipolar transistor included within the power clamp circuit.

Abstract: An ESD protection circuit includes: a voltage decreasing module, coupled between a first voltage level and a second voltage level, wherein the first voltage level is higher than the second voltage level; a gate trigger switch, coupled between the first voltage level and the second voltage level; and a detection circuit, coupled to the gate trigger switch, for detecting an ESD event to control the gate trigger switch.