Patents by Inventor Kun Yi

Kun Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973192
    Abstract: The invention provides an electrode body for a cylindrical lithium battery, which is formed by winding a laminated body including a negative electrode sheet, a first separator, a positive electrode sheet, a plurality of cathode tabs and a plurality of anode tabs, wherein the negative sheet and the positive sheet have a negative electrode coating and a positive electrode coating, respectively. In the present invention, the positive electrode coating is provided on the positive electrode sheet in a specific configuration to increase the coating area of the positive electrode coating, thereby increasing the capacitance of the electrode body.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: April 30, 2024
    Assignee: E-ONE MOLI ENERGY CORP.
    Inventors: Jui-Min Tsai, Tsung-Yi Tsai, Kun-Miao Tsai, Wei-Dung Chang
  • Patent number: 11967504
    Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Jia-Ming Lin, Kun-Yu Lee, Chi On Chui
  • Publication number: 20240128876
    Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.
    Type: Application
    Filed: June 15, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
  • Publication number: 20240120845
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240120844
    Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 11, 2024
    Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
  • Publication number: 20240120846
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240121027
    Abstract: Provided are a data processing system and method based on dynamic redundancy heterogeneous encoding, and a device. The method comprises: respectively performing error correction encoding on information to be processed and a processing rule, so as to form encoded information to be processed and an encoded processing rule; processing, by using the encoded processing rule, the encoded information to be processed, so as to obtain response data; and then performing error correction decoding on N pieces of response data, so as to obtain processing result information of the information to be processed.
    Type: Application
    Filed: June 7, 2021
    Publication date: April 11, 2024
    Inventors: Lei HE, Jiangxing WU, Quan REN, Peng YI, Xiang CHEN, Jing YU, Kun ZHOU, Yiwei GUO, Zhifeng FENG
  • Publication number: 20240103626
    Abstract: The disclosed apparatus may include a wearable haptic ring that features input capabilities relative to a computing system. In various examples, the wearable haptic ring may be designed to curve around a human finger of a wearer with a touchpad that is seamlessly integrated with the ring. For example, the seamlessly integrated touchpad may be operable by another finger of the wearer. Moreover, the haptic ring may include a haptic feedback unit designed to provide haptic feedback in response to input from the wearer. As such, the haptic ring may enable a wide range of user inputs while appearing like a typical ring rather than a computer input/output device. Various other implementations are also disclosed.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 28, 2024
    Inventors: Dan Kun-yi Chen, Chengyuan Yan
  • Publication number: 20240078345
    Abstract: A method for tamper protection in cryptographic calculations is provided. A cryptographic calculation includes a plurality of normal rounds and a plurality of redundant rounds. The method includes obtaining a first variable x and a second variable y using a random number generator; dividing the normal rounds into a first normal section and a second normal section, and dividing the redundant rounds into a first redundant section and a second redundant section according to the first variable x and the second variable y; executing the first normal section and the first redundant section in sequence using a clock signal; in response to completion of the first redundant section and a first calculation result of the first normal section and a second calculation result of the first redundant section being the same, executing the second normal section and the second redundant section in sequence to complete the cryptographic calculation.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 7, 2024
    Inventors: Kun-Yi WU, Yu-Shan LI
  • Publication number: 20240079493
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: GUAN-QI CHEN, CHEN CHI HSIAO, KUN-TSANG CHUANG, FANG YI LIAO, YU SHAN HUNG, CHUN-CHIA CHEN, YU-SHAN HUANG, TUNG-I LIN
  • Publication number: 20240054352
    Abstract: A multi-layer federated learning method based on distributed clustering is provided, which comprises the following steps. Computing a feature distribution similarity for each of participating nodes with non-(non-independent and identically distributed) data sets, and grouping these nodes into plural clusters by the feature distribution similarity. Updating local model of nodes of each cluster by a federated learning algorithm, and inputting these nodes into a multi-layer aggregation mechanism. Terminating the operation of the multi-layer aggregation mechanism until the clustering result meets a required demand. Furthermore, we implement a blockchain-based multi-layer federated learning system, including model aggregation module, API module, time-series synchronization module, and IPFS, based on distributed clustering architecture. The learning performance is proven to effectively improved.
    Type: Application
    Filed: July 30, 2023
    Publication date: February 15, 2024
    Applicant: ASIA UNIVERSITY
    Inventors: ZON-YIN SHAE, KUN-YI CHEN, JING-PHA TSAI, CHI-YU CHANG, YUAN-YU TSAI
  • Publication number: 20240007283
    Abstract: A cryptographic device for a memory device includes a determination unit, a mapping unit, and a cryptographic unit. The determination unit determines that a memory address is in a protection area to select a key and a random number. The mapping unit maps a binary code to an injection code according to the key and the memory address, in which the binary code includes the random number and the memory address. The cryptographic unit generates a key stream according to the key and the injection code.
    Type: Application
    Filed: May 30, 2023
    Publication date: January 4, 2024
    Inventors: Shun-Hsiung CHEN, Kun-Yi WU, Yu-Shan LI
  • Publication number: 20230418912
    Abstract: A medical data ownership management method comprises: Granting a first authority to a medical unit where the first authority allows the medical unit to generate a first medical object with its corresponding first non-fungible token (NFT) storing on a blockchain. Granting a second authority to a research unit, where the second authority allows the research unit to access the first medical object, and the research unit processes the first medical object to generate the second medical object with its corresponding second NFT storing on the blockchain. Finally, granting a third authority to a user unit, where the third authority allows the user unit to access the second medical object. The access control and ownership transfer of each medial object in the blockchain are achieved by trading the corresponding NFT and modifying its subordinate list. With the management method, the security and the privacy of the medical data will be enhanced.
    Type: Application
    Filed: October 14, 2022
    Publication date: December 28, 2023
    Inventors: ZON-YIN SHAE, JING-PHA TSAI, CHI-YU CHANG, YUAN-YU TSAI, KUN-YI CHEN
  • Publication number: 20230380293
    Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 23, 2023
    Inventors: JIANN-HORNG LIN, KUN-YI LI, HAN-TING LIN, HUAN-JUST LIN, CHEN-JUNG WANG, SIN-YI YANG
  • Publication number: 20230327867
    Abstract: An encryption device is provided, which includes a controller, a random controller, a first functional unit, and a second functional unit. The controller generates a first enable signal and a second enable signal. When at least one of the first enable signal and the second enable signal is in a first logic level, the random controller generates a first random signal and a second random signal. The first functional unit performs the corresponding operation according to the first enable signal and the first random signal. The second functional unit performs the corresponding operation according to the second enable signal and the second random signal.
    Type: Application
    Filed: November 9, 2022
    Publication date: October 12, 2023
    Inventors: Kun-Yi WU, Yu-Shan LI
  • Patent number: 11770977
    Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiann-Horng Lin, Kun-Yi Li, Han-Ting Lin, Huan-Just Lin, Chen-Jung Wang, Sin-Yi Yang
  • Publication number: 20230214216
    Abstract: An addition mask value generator is provided. A first operation circuit is configured to obtain first intermediate data according to first output mask value and fourth output mask value. A second operation circuit is configured to obtain the addition output mask value of a first mask group according to first intermediate data and fourth input mask value. A third operation circuit is configured to obtain second intermediate data according to second output mask value and third output mask value. A fourth operation circuit is configured to obtain the addition output mask value of a second mask group according to second intermediate data and second input mask value. The first and second addition input mask values of first mask group are first and second input mask values. The first and second addition input mask values of second mask group are third input mask value and first intermediate data.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 6, 2023
    Inventors: Kun-Yi WU, Yu-Shan LI
  • Publication number: 20230214183
    Abstract: A carry-lookahead adder is provided. First XOR gate receives a first mask value and a second mask value to provide a variable. First mask unit performs a first mask operation on first input data with the variable to obtain first masked data. A half adder receives the first masked data and second input data to generate a propagation value and an intermediate generation value. Second mask unit performs a second mask operation on the propagation value with a third mask value to obtain second masked data. A logic circuit provides a generation value according to the propagation value, the intermediate generation value and the second mask value. A carry-lookahead generator provides a carry output and a carry value according to a carry input, the generation value and the propagation value. Second XOR gate receives the second masked data and the carry value to provide a sum output.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 6, 2023
    Inventors: Kun-Yi WU, Yu-Shan LI
  • Publication number: 20230216677
    Abstract: A cipher accelerator is provided. An encryption and decryption circuit is configured to perform an encryption and decryption operation according to a control signal. The encryption and decryption operation includes a plurality of normal rounds and a plurality of redundant rounds. A controller is configured to provide a control signal to the encryption and decryption circuit according to a first variable value and a second variable value. The encryption and decryption circuit is configured to divide the normal rounds into a first normal section and a second normal section according to the first variable value, and divide the redundant rounds into a first redundant section and a second redundant section according to the second variable value. The encryption and decryption circuit is configured to perform the first normal section, the first redundant section, the second normal section, and the second redundant section sequentially.
    Type: Application
    Filed: November 9, 2022
    Publication date: July 6, 2023
    Inventors: Kun-Yi WU, Yu-Shan LI
  • Publication number: 20230214189
    Abstract: A carry-lookahead adder is provided. A first mask unit performs first mask operation on first input data with the first mask value to obtain first masked data. A second mask unit performs second mask operation on second input data with the second mask value to obtain second masked data. A first XOR gate receives the first and second mask values to provide a variable value. A half adder receives the first and second masked data to generate a propagation value and an intermediate generation value. A third mask unit performs third mask operation on the propagation value with the third mask value to obtain the third masked data. A carry-lookahead generator provides the carry output and the carry value according to carry input, the generation value, and the propagation value. The second XOR gate receives the third masked data and the carry value to provide the sum output.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 6, 2023
    Inventors: Kun-Yi WU, Yu-Shan LI