Abstract: The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.

Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and a hard mask atop the metal gate; and performing a high-density plasma (HDP) process to form a cap layer on the hard mask and the substrate.

Abstract: A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, and a first metal plug structure, wherein a circuit element is disposed on the substrate. The first dielectric layer is disposed on the circuit element and on the substrate. The first metal plug structure, including a first barrier metal layer and a first metal interconnector, is embedded in the first dielectric layer. The first metal interconnector is in direct contact with the circuit element. The first barrier metal layer is disposed on the first metal interconnector; wherein the first barrier metal layer and the first metal interconnect have different metal materials.

Abstract: The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a device thereon; forming a dielectric layer on the device and the substrate; forming a first mask layer on the dielectric layer; removing part of the first mask layer and part of the dielectric layer for forming a patterned first mask layer on the dielectric layer; covering a hard mask on the patterned first mask layer and the dielectric layer; partially removing the hard mask for forming a spacer adjacent to the patterned first mask layer and the dielectric layer; forming a contact hole adjacent to the spacer; filling the contact hole with a metal layer; and planarizing the metal layer for forming a contact plug, wherein the contact plug contacts the dielectric layer and the spacer simultaneously.

Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.

Abstract: A method of forming a semiconductor device having a metal gate includes the following steps. First of all, a first gate trench is formed in a dielectric layer. Next, a first work function layer is formed, covering the first gate trench. Then, a protection layer is formed in the first gate trench, also on the first work function layer. Then, a patterned sacrificial mask layer is formed in the first gate trench to expose a portion of the protection layer. After that, the exposed protection layer is removed, to form a U-shaped protection layer in the first gate trench. As following, a portion of the first work function layer under the exposed protection layer is removed, to form a U-shaped first work function layer in the first gate trench. Finally, the patterned sacrificial mask layer and the U-shaped protection layer are completely removed.

Abstract: A method of forming a contact hole includes providing a substrate. A nitrogen-containing dielectric layer, a first material layer, a second material layer, an oxygen-containing dielectric layer and a patterned photoresist layer cover the substrate from bottom to top. Then, the oxygen-containing dielectric layer is etched by taking the second material layer as a first etching stop layer to form a patterned oxygen-containing dielectric layer. Latter, the second material layer is etched by taking the first material layer as a second etching stop layer to form a patterned second material layer. Subsequently, the first material layer is etched by taking the nitrogen-containing dielectric layer as a third etching stop layer to form a patterned first material layer. Finally, the nitrogen-containing dielectric layer is etched until the substrate is exposed.

Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Abstract: A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.

Abstract: A single-wafer cleaning procedure has the steps of providing an etched wafer comprising a photo resist pattern on a front surface of the etched wafer, performing an ashing process to remove the photo resist pattern, hoisting the etched wafer to cool down the etched wafer, and performing a dry cleaning process upon the hoisted etched wafer when the etched wafer is cooled down.

Abstract: A single-wafer dry cleaning procedure. First, an etched wafer having a photo resist pattern thereon is provided. Then, an ashing process is performed to remove the photo resist pattern. Finally, the etched wafer is hoisted and maintained in a suspended condition, a dry cleaning process then being performed upon the etched wafer.

Abstract: A method of manufacturing a metal oxide semiconductor device, wherein a gate dielectric layer, a conductive layer and a patterned mask layer are successively formed on the substrate. Using the mask layer as a mask, the conductive layer is slant-etched and the remaining portion of the conductive layer becomes a spacer wall of a gate and between the two sides of the gate, and exposes a portion of the gate dielectric layer. The gate is located directly below the mask layer. Using the mask layer and the spacer wall as a mask, ion implantation is performed, thereby forming a source/drain region within the substrate between the two sidewalls of the spacer walls. An annealing process is performed. Using the mask layer as a mask to etch away the spacer wall, a lightly doped drain is formed with the substrate between the two sidewalls of the gate, thereby completing a MOS device.