Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: One embodiment of the present invention provides techniques and systems for modeling long-range extreme ultraviolet lithography (EUVL) flare. During operation, the system may receive an evaluation point in a layout. Next, the system may receive an EUVL model which includes kernels that are discretized at different sampling rates, and which have different sized ambits. Specifically, a kernel that is discretized using a low sampling rate may have a longer range than a kernel that is discretized using a high sampling rate. The system may then convolve the kernels with the layout at the evaluation point over their respective ambits. Next, the system may use the convolution results to determine an indicator value. The indicator value can be used for a number of applications, e.g., to predict pattern shapes that are expected to print on a wafer, to perform optical proximity correction, or to identify manufacturing problem areas in the layout.

Abstract: One embodiment of the present invention provides techniques and systems for modeling long-range extreme ultraviolet lithography (EUVL) flare. During operation, the system may receive an evaluation point in a layout. Next, the system may receive an EUVL model which includes kernels that are discretized at different sampling rates, and which have different sized ambits. Specifically, a kernel that is discretized using a low sampling rate may have a longer range than a kernel that is discretized using a high sampling rate. The system may then convolve the kernels with the layout at the evaluation point over their respective ambits. Next, the system may use the convolution results to determine an indicator value. The indicator value can be used for a number of applications, e.g., to predict pattern shapes that are expected to print on a wafer, to perform optical proximity correction, or to identify manufacturing problem areas in the layout.

Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.

Abstract: A system, apparatus and/or method is provided for fabricating an integrated capacitor during the fabrication of a transistor employing chemical mechanical polishing of a gate electrode of the transistor. Components of the integrated capacitor, particularly the lower electrode of a parallel plate capacitor in one form thereof, and an outer plate of a cylindrical-like capacitor in another form thereof, are defined by the polish stop layer during chemical mechanical polishing (CMP) of a gate of the transistor. According to an aspect of the subject invention, the polish stop layer may be an oxide or a nitride.

Abstract: A phase shift mask having transmission properties that are dependent at least in part on an intensity of an incident light beam. The phase shift mask has a mask substrate that is substantially transparent to the incident light beam. A first phase shift layer is disposed on the mask substrate. The first phase shift layer has a refractive index that is nonlinear with the intensity of the incident light beam. The refractive index of the first phase shift layer changes with the intensity of the incident light beam on the phase shift mask. By using a first phase shift layer on the phase shift mask that has a refractive index that is non linear with the intensity of the incident light beam, properties of a light beam transmitted through the first phase shift layer, such as interference patterns in the transmitted light beam, can be adjusted by adjusting the intensity of the incident light beam.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: An arrangement for controlling the transmission of a light signal is disclosed. The arrangement includes a first fiber optic line for transmitting the light signal and a light receiving unit operatively coupled to the first fiber optic line so that the light signal is received by the light receiving unit. The light receiving unit is operative to refract the light signal so that the light signal is substantially prevented from being transmitted through the light receiving unit if an intensity level of the light signal has a predetermined relationship with an intensity threshold level.

Abstract: A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than ?rd of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed.

Abstract: A phase shift mask having transmission properties that are dependent at least in part on an intensity of an incident light beam. The phase shift mask has a mask substrate that is substantially transparent to the incident light beam. A first phase shift layer is disposed on the mask substrate. The first phase shift layer has a refractive index that is nonlinear with the intensity of the incident light beam. The refractive index of the first phase shift layer changes with the intensity of the incident light beam on the phase shift mask. By using a first phase shift layer on the phase shift mask that has a refractive index that is non linear with the intensity of the incident light beam, properties of a light beam transmitted through the first phase shift layer, such as interference patterns in the transmitted light beam, can be adjusted by adjusting the intensity of the incident light beam.

Abstract: A system, apparatus and/or method is provided for fabricating an integrated capacitor during the fabrication of a transistor employing chemical mechanical polishing of a gate electrode of the transistor. Components of the integrated capacitor, particularly the lower electrode of a parallel plate capacitor in one form thereof, and an outer plate of a cylindrical-like capacitor in another form thereof, are defined by the polish stop layer during chemical mechanical polishing (CMP) of a gate of the transistor. According to an aspect of the subject invention, the polish stop layer may be an oxide or a nitride.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: A substantially vertical interdigitated plate capacitor, formed in interlayer dielectric material between upper and lower interconnect layers of conductors in an integrated circuit, comprising a lower plate that has at least one U-shaped portion and a horizontal portion connected to an upper edge of the U-shaped portion. The capacitor's upper plate also has at least one U-shaped portion positioned within the interior of the lower plate's U-shaped portion and a horizontal portion connected to an upper edge of each vertically extending leg. The integrated circuit incorporating the capacitor comprises a via connection having a U-shaped layer extending between the conductors of the relatively upper and relatively lower interconnect layers and is formed simultaneously with one of the U-shaped portions of the capacitor plates.

Abstract: A method of forming a semiconductor device on a substrate comprising the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.

Abstract: A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than ⅓rd of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed.

Abstract: A method of fabricating a semiconductor wafer having an active area and an inactive outer clear out area includes the step of fabricating a number of active dies on a first side of the wafer such that each of the number of active dies is completely contained within the active area of the wafer. The method also includes the step of generating a laser beam with a laser device. Moreover, the method includes the step of scribing a code in the inactive outer clear out area of the wafer with the laser beam such that the code is completely contained within the inactive outer clear out area of the wafer. An apparatus for scribing a code in an inactive outer clear out area of a first side of a semiconductor wafer is also disclosed.

Abstract: A method of exposing an alignment mark defined in a first side of a semiconductor wafer includes the step of engaging a second side of the wafer with a wafer chuck. The method also includes the step of positioning the wafer in a chamber having a photochemical reactant gas present therein during the engaging step. Moreover, the method includes the step of impinging laser beams on the first side of the wafer such that a reactant specie is generated from the photochemical reactant gas. Yet further, the method includes the step of removing material from the first side of the wafer with the reactant specie. An apparatus for exposing an alignment mark defined in a first side of a semiconductor wafer is also disclosed.

Abstract: An apparatus for polishing a first side of a semiconductor wafer down to a desired level includes a polishing platen having a polishing surface. The apparatus also includes a wafer carrier having a first sub-carrier and a second sub-carrier which is concentric to the first sub-carrier. The first sub-carrier is configured to engage a first radial portion of the wafer by a second side of the wafer and apply first pressure to the first radial portion in order to press the first radial portion against the polishing surface of the polishing platen. The second sub-carrier is configured to engage a second radial portion of the wafer by the second side of the wafer and apply second pressure to the second radial portion in order to press the second radial portion against the polishing surface of the polishing platen.