Abstract: A method of forming a semiconductor device on a substrate including the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.

Abstract: A photolithography apparatus for deep UV enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. this photolithography apparatus employs a different approach to contrast enhancement which is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than ⅓rd of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed.

Abstract: A vertical plate capacitor is formed in interlayer dielectric material which separates conductors of upper and lower interconnect layers by a method which avoids the accumulation of residual materials from chemical mechanical polishing (CMP). The method comprises the steps of forming a capacitor via into the interlayer dielectric material, forming a first conductive layer having a U-shaped portion into the capacitor via, forming U-shaped capacitor dielectric material in the U-shaped portion of the first conductive layer, forming a second conductive layer having a U-shaped portion in the U-shaped capacitor dielectric material, filling an interior of the U-shaped portion of the second conductive layer with a plug material, and polishing after the capacitor via is entirely occupied by these elements.

Abstract: A method of exposing an alignment mark defined in a first side of a semiconductor wafer includes the step of engaging a second side of the wafer with a wafer chuck. The method also includes the step of positioning the wafer in a chamber having a photochemical reactant gas present therein during the engaging step. Moreover, the method includes the step of impinging laser beams on the first side of the wafer such that a reactant specie is generated from the photochemical reactant gas. Yet further, the method includes the step of removing material from the first side of the wafer with the reactant specie. An apparatus for exposing an alignment mark defined in a first side of a semiconductor wafer is also disclosed.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: An apparatus for etching a first side of a semiconductor wafer down to a desired level. The apparatus includes an etching chamber. The apparatus also includes a wafer chuck configured to engage the wafer by a second side of the wafer, and position the wafer in the etching chamber. The apparatus also includes a light source unit positioned such that light signals generated by the light source unit are directed into the wafer. Moreover, the apparatus includes a light receiving unit positioned such that the light signals generated by the light source unit emanate out of the wafer and are received with the light receiving unit. The light receiving unit includes a first optical material and a second optical material having an interface therebetween. The first optical material has a linear index of refraction, whereas the second optical material has a nonlinear index of refraction which is dependent on an intensity level of the light signals received with the light receiving unit.

Abstract: An apparatus for use in the deposition of oxide on a wafer, the apparatus including a chamber for receiving oxygen gas that is used for forming the oxide on the wafer, the apparatus comprising: a wafer chuck located within the chamber, the wafer chuck capable of supporting the wafer during the deposition of oxide on the wafer; and an oxide blocking member located within the chamber and detached from the wafer, the oxide blocking member capable of preventing the deposition of oxide in at least one predetermined area of the wafer.

Abstract: An apparatus for polishing a first side of a semiconductor wafer down to a desired level includes a polishing platen having a polishing surface. The polishing platen has a light egress opening defined therein. The apparatus also includes a wafer carrier which is configured to engage the wafer by a second side of the wafer and apply pressure to the wafer in order to press the wafer against the polishing surface of the polishing platen, wherein the wafer carrier has a light-ingress opening defined therein. The apparatus further includes an infrared light source unit positioned such that light signals generated by the infrared light source unit are directed out the light egress opening and into the wafer. The apparatus yet further includes a light receiving unit positioned such that the light signals generated by the infrared light source unit emanate out of the wafer and are received with the light receiving unit.