Abstract: A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material, and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure to are removed to expose the doped semiconductive material.

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.