Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Abstract: A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprises decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another, at least one of the at least two different decomposition species comprising Si. An outer substrate surface is contacted with the at least two decomposition species. At least one of the decomposition species that comprises Si attaches to the outer substrate surface to comprise an attached species. The attached species is contacted with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3. Other embodiments are disclosed, including constructions made in accordance with method embodiments of the invention and constructions independent of method of manufacture.

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.