Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Abstract: A slim vapor chamber includes a first plate, a second plate and a capillary structure. The periphery of the second plate is connected with that of the first plate to form a chamber. The capillary structure is disposed on an inner wall of the chamber. Both of a side of the first plate facing the second plate and a side of the second plate facing the first plate are formed with a plurality of supporting structures, which include a plurality of supporting pillars and a plurality of supporting plates, by an etching process.

Abstract: The disclosure provides an electronic device including a support plate and a first panel. The support plate includes a first bridge member and a second bridge member. The first panel is disposed on the support plate and includes a substrate, a signal line, a third bridge member, and a fourth bridge member. The signal line is disposed on the substrate. The third bridge member penetrates through the substrate and is electrically connected to the signal line and the first bridge member. The fourth bridge member penetrates through the substrate and is electrically connected to the signal line and the second bridge member.

Abstract: A driving circuit for driving a light emitting unit is provided. The driving circuit includes a driving transistor, a switch transistor, an emitting transistor, a first capacitor and a first compensation transistor. The switch transistor is coupled to the driving transistor. The emitting transistor is coupled between the light emitting unit and the driving transistor. The first capacitor is coupled to the driving transistor. The first compensation transistor is coupled to the first capacitor. A first end of the first compensation transistor and a first end of the emitting transistor receive same signal.

Abstract: A heat pipe comprises a first pipe and at least a second pipe. The first pipe includes an evaporator, a heat insulator and a condenser communicating with each other to define a hollow chamber. The second pipe disposed in the hollow chamber includes an accommodating space and a first capillary structure disposed in one end of the accommodating space closer to the evaporator. At least one side of an outer pipe wall of the second pipe directly abuts an inner pipe wall of the first pipe. The first pipe further includes a second capillary structure disposed in the hollow chamber closer to the evaporator and extended to an outside of the second pipe and occupies at least 2/3 volume of the evaporator. A first part of the first capillary structure and the second capillary structure are connected to each other by winding so as to enhance transportation therebetween.

Abstract: The disclosure provides an electronic device including a pixel circuit and a protection circuit. The pixel circuit includes a driving transistor. The protection circuit includes a first connection transistor, a first switching transistor, and a logic circuit. The first connection transistor is coupled to the driving transistor. The first switching transistor is coupled to the first connection transistor. The logic circuit is coupled to the first switching transistor. The electronic device of the disclosure may provide a pixel protection function through the protection circuit coupled with the pixel circuit.

Abstract: A driving circuit includes a first transistor, a second transistor and a third transistor. The first transistor has a first terminal connected to a first voltage level, a second terminal, and a third terminal The second transistor has a first terminal connected to the second terminal of the first transistor, a second terminal connected to a second voltage level, and a third terminal connected to the third terminal of the first transistor. The third transistor has a first terminal connected to the first terminal of the second transistor. The first transistor and the second transistor are low temperature poly-silicon transistors, and the third transistor is an oxide semiconductor transistor.

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.

Abstract: A method and an electronic device for selecting influence indicators by using an automatic mechanism are provided. The method includes following steps. Raw data is obtained, where the raw data includes a body-related variable and a plurality of to-be-measured indicators corresponding to the body-related variable. The body-related variable is set as a target parameter. The body-related variable and the to-be-measured indicators are input into a plurality of validation models, and the to-be-measured indicators are sorted according an output result of the validation models to obtain ranking data. Importance of the to-be-measured indicators is calculated by using a screening condition according to the ranking data, so as to select a candidate indicator from the to-be-measured indicators. An influence indicator is determined by calculating a correlation between the candidate indicator and the body-related variable.

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Abstract: A test head assembly for a semiconductor device has a carrier, a pin seat and a test wire assembly. The carrier is formed in an L shape and has a lateral board, a perpendicular board and a opening formed through the perpendicular board. The pin seat is mounted in the corresponding opening. The test wire assembly has a teat head, a plurality of connectors and a plurality of test wires. The test head is mounted on an outer sidewall of the lateral board and connected to the pin seat through the test wires and the connectors. Therefore, the pin seat is mounted on the perpendicular board of the L-shaped uprightly and the test head is mounted on the lateral board. The pin seat and the test head are not parallel to each other, and a lateral size of the test head assembly is reduced to increase the space usage.

Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure. The first stacked die package structure includes a plurality of memory dies. The underfill layer is over the first stacked die package structure. The underfill layer includes a first protruding portion that extends below a top surface of the through substrate via structure. The package layer is over the underfill layer. The package layer has a second protruding portion that extends below the top surface of the through substrate via structure.

Abstract: A heat pipe comprises a first pipe and at least a second pipe. The first pipe includes an evaporator, a heat insulator and a condenser communicating with each other to define a hollow chamber. The second pipe disposed in the hollow chamber includes an accommodating space and a first capillary structure disposed in one end of the accommodating space closer to the evaporator. Two opposite sides of an outer pipe wall of the second pipe directly abut an inner pipe wall of the first pipe. The first pipe further includes a second capillary structure which is disposed in the hollow chamber closer to the evaporator and extended to an outside of the second pipe and occupies at least ? volume of the evaporator. A first part of the first capillary structure and the second capillary structure are connected to each other by winding so as to enhance transportation therebetween.

Abstract: A model training method and an electronic device are provided. The method includes the following steps: establishing a brain age prediction model according to a training set; adjusting a parameter in the brain age prediction model according to a validation set; inputting a test set into the brain age prediction model with the adjusted parameter to obtain a plurality of first predicted brain ages; determining whether the first predicted brain ages satisfy a first specific condition; and completing training of the brain age prediction model when the first predicted brain ages satisfy the first specific condition.

Abstract: A driving circuit includes a first transistor having a first terminal, a second terminal and a control terminal; a second transistor having a first terminal connected to the second terminal of the first transistor and a second terminal connected to an organic light-emitting diode; a third transistor having a first terminal connected to the control terminal of the first transistor; a fourth transistor having a first terminal connected to the first terminal of the first transistor; and a fifth transistor having a first terminal connected to the second terminal of the second transistor. The first transistor, the second transistor and the fourth transistor are low temperature poly-silicon transistors, and the third transistor is an oxide semiconductor transistor.

Abstract: A medication risk evaluation method and a medication risk evaluation device are provided. The medication risk evaluation method includes: obtaining first medication route information related to a first medicine combination in a medication database; obtaining second medication route information related to a second medicine combination in the medication database; obtaining overlapping medication information between the first medication route information and the second medication route information; determining whether the overlapping medication information meets a noise exclusion condition; and if the overlapping medication information meets the noise exclusion condition, establishing a risk evaluation model based on other medication route information in the medication database excluding the first medication route information, where the risk evaluation model is adapted to evaluate a risk of using at least one medicine in the medication database.

Abstract: A display device includes: a substrate; a data line disposed on the substrate; an another data line disposed on the substrate and adjacent to the data line; a first light emitting diode including a first electrode; and a second light emitting diode including an another first electrode, wherein the first electrode partially overlaps the data line, the another first electrode partially overlaps the another data line, and an area of the first electrode and an area of the another first electrode are different.

Abstract: A method for calculating a high risk route of administration is provided. Multiple arrangement routes composed of every two medicines among multiple medicines included in a medical record database are listed. A risk value of each arrangement route is calculated by querying the medical record database based on a specified medication result. A risk score of each arrangement route is calculated according to the risk value, and the arrangement routes are sorted based on the risk scores. Starting from the arrangement route with the highest risk score, N arrangement routes are retrieved and a combination on N of the arrangement routes is performed to obtain multiple strung routes. The number of medicines included in each strung route matches a specified medication number.