Patents by Inventor Kunihiko Iizuka
Kunihiko Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6983011Abstract: In a filter circuit of the present invention, a partial quantization value is computed by a quantization circuit according to a spread code and others in a unit at an arbitrary stage, where an integrating value is increased. The partial quantization value is successively added by an adder formed by a counter and is transmitted to a unit of the following stage. In an adder of the following stage, an analog residual is computed by subtracting an analog converted value of the partial quantization value, that is obtained by a D/A converter, from the integrating value so as to suppress an increase in the analog cumulative value. With this arrangement, the cumulative value is increased according to an increase in the number of taps, so that an analog adder can reduce power consumption, which is caused by expansion of a dynamic range at the following stage.Type: GrantFiled: June 22, 2000Date of Patent: January 3, 2006Assignee: Sharp Kabushiki KaishaInventors: Keita Hara, Kunihiko Iizuka
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Publication number: 20050186935Abstract: A wireless receiving circuit includes a mixer, a buffer, an active low-pass filter, and a second order passive low-pass filter which are connected between a signal input terminal and a signal output terminal. The second order passive low-pass filter is for removing an interfering wave that cannot be removed by the active low-pass filter. In the wireless receiving circuit, a first capacitor and a second capacitor are provided. The first capacitor has one terminal connected to an input terminal of the buffer and the other terminal grounded. The second capacitor has one terminal connected to an output terminal of the buffer and the other terminal grounded. These two kinds of capacitors function as the second order passive low-pass filter by being combined with input and output impedance of elements provided on the upstream side and downstream side of the capacitors.Type: ApplicationFiled: February 22, 2005Publication date: August 25, 2005Inventors: Shuichi Kawama, Kunihiko Iizuka
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Publication number: 20050089122Abstract: A correlator which can be adapted to a receiver for impulse radio includes a multiplier for multiplying a received impulse train by a received template train, an analog integrator for integrating the result of the multiplication, and a quantizer quantizing the result of the integration, which result is supplied to a digital integrator. An adder is provided on the input side of the analog integrator, and a negative feedback path negatively feeds the result of the quantization back to the analog integrator via the adder. Quantization errors occurring in the quantizer are negatively fed back to the analog integrator and thereby integrated, then quantized by the quantizer again. As a result, it is possible to reduce quantization errors and to improve the S/N ratio.Type: ApplicationFiled: July 25, 2003Publication date: April 28, 2005Inventor: Kunihiko Iizuka
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Patent number: 6844354Abstract: An agent for the prophylaxis and treatment of interstitial pneumonia and pulmonary fibrosis, which contains a compound having a Rho kinase inhibitory activity, particularly an agent for the prophylaxis and treatment of interstitial pneumonia and pulmonary fibrosis, which contains a compound of the formula (I) wherein each symbol is as defined in the specification, as the compound having a Rho kinase inhibitory activity, is provided.Type: GrantFiled: March 21, 2000Date of Patent: January 18, 2005Assignee: Mitsubishi Pharma CorporationInventors: Kunihiko Iizuka, Kunio Dobashi, Masayoshi Uehata
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Publication number: 20040196936Abstract: A switched capacitor filter having an anti-aliasing function includes integration circuits of multiple-stages, each of which is provided with an amplifier and a switched capacitor. At least an integration circuit of the first stage has a resistor. In the filter, bipolar transistors are used for the input stage of an amplifier in at least one of the integration circuits having a resistor. On the account of this, 1/f noise is reduced.Type: ApplicationFiled: March 18, 2004Publication date: October 7, 2004Inventors: Shuichi Kawama, Shinichiro Azuma, Kunihiko Iizuka
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Patent number: 6788736Abstract: A matched filter for inversely spreading a received signal using spreading signals in a spread spectrum communications receiver includes: a plurality of correlators for determining cross-correlation functions of a received signal which has been sampled at a certain timing and spreading signals having a certain section length; a delay circuit for successively transferring the spreading signals having a certain section length with respect to the plurality of correlating means by delaying timings of the transfer by a period equal to the section length of the spreading signals; and a multiplexer for successively selecting one of the cross-correlation functions outputted from the plurality of correlating means, by a period equal to a sampling interval of the received signal. As a result, a matched filter with a small circuit size and low power consumption is realized.Type: GrantFiled: August 17, 1999Date of Patent: September 7, 2004Assignee: Sharp Kabushiki KaishaInventors: Shuichi Kawama, Kunihiko Iizuka
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Patent number: 6697444Abstract: An analog input signal that is sampled at a predetermined rate is multiplied by a corresponding binary code sequence, i.e. “+1” or “−1” by the multiplier. The output of this multiplier is applied in conjunction with a signal supplied by the negative feed back circuit to the analog integrator. The quantization circuit quantizes the output signal of the analog integrator into N levels and outputs a digital word. This digital word is delayed by a unit time interval by a digital delay circuit and then processed by the above mentioned negative feed back circuit. As a result of this signal magnitude reducing process, the required integrating capacitance can be minimized without risks of saturation effects. Additionally, the output is already in digital form as required by the subsequent system blocks.Type: GrantFiled: February 8, 2000Date of Patent: February 24, 2004Assignees: Sharp Kabushiki Kaisha, Synchro Design Inc.Inventors: Kunihiko Iizuka, Daniel Senderowicz
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Patent number: 6493404Abstract: An analog input signal that is sampled at a predetermined rate is multiplied by a corresponding binary code sequence, i.e. “+1” or “−1” by the multiplier. The output of this multiplier is applied in conjunction with a signal supplied by the negative feedback circuit to the analog integrator. The quantization circuit quantizes the output signal of the analog integrator into N levels and outputs a digital word. This digital word is delayed by a unit time interval by a digital delay circuit and then processed by the above mentioned negative feedback circuit. As a result of this signal magnitude reducing process, the required integrating capacitance can be minimized without risks of saturation effects. Additionally, the output is already in digital form as required by the subsequent system blocks.Type: GrantFiled: March 1, 1999Date of Patent: December 10, 2002Assignees: Sharp Kabushiki Kaisha, Synchro DesignInventors: Kunihiko Iizuka, Daniel Senderowicz
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Publication number: 20020019974Abstract: A program development device provides functions of developing an unitarily designed application program even when utilizing components, in which a multiplicity of interfaces can be used, and a multiplicity of combinations of these components can be provided. The program development device (1, 10)) for developing the application program by use of the component having the plurality of interfaces, includes a component selecting module (101) for having the component selected, an interface selection module (102, 103) for having the interface selected for the selected component, and setting the selected interface in a valid or invalid state, a recording unit (4) for retaining a set record (11) of having set the interface in the valid or invalid state, and a edit module (120) for supporting the development of the program by use of the interface set in the valid state or the interface that is not set in the invalid state in accordance with the set record.Type: ApplicationFiled: February 20, 2001Publication date: February 14, 2002Inventor: Kunihiko Iizuka
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Patent number: 6301294Abstract: A spread spectrum communication device incorporates a base band processing unit which includes a synchronization acquiring section for acquiring synchronization with respect to an analog spread spectrum signal and a data demodulating section for conducting a demodulating operation with respect to the analog spread spectrum signal which has been subject to the synchronization acquiring operation by the synchronization acquiring section. The synchronization acquiring section has a matched filter for detecting a peak position of the analog spread spectrum signal inputted thereto, and at least the operation of the matched filter is an analog processing operation.Type: GrantFiled: September 29, 1998Date of Patent: October 9, 2001Assignee: Sharp Kabushiki KaishaInventors: Keita Hara, Kunihiko Iizuka
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Patent number: 6166676Abstract: In a correlating device, two switched-capacitor-type analog signal integrators are connected in cascade. The analog signal integrator in the first stage samples an analog input voltage at a predetermined cycle, determines the sign of the sampled value according to a binary-code sequence, integrates the sampled value, and outputs the resultant value. The analog signal integrator in the next stage samples an input voltage at a reset cycle of the analog signal integrator in the first stage, integrates the sampled value, and outputs the resultant value. This structure can prevent saturation of the correlating device without decreasing the gain of each analog signal integrator to a greet degree even when the sequence length becomes longer.Type: GrantFiled: October 27, 1998Date of Patent: December 26, 2000Assignee: Sharp Kabushiki KaishaInventor: Kunihiko Iizuka
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Patent number: 5960033Abstract: A sample-hold circuit, which is constituted by a capacitor and a differential amplifier or a capacitor and an inversion amplifier, is provided with a first switch for short-circuiting the input and output, a second switch for switching the input-side terminal of the input capacitor to a reference voltage input, a third switch for switching the output-side terminal of the feedback capacitor to the reference voltage input, and a fourth switch for switching the input-side terminal of the input capacitor to an input voltage; thus a refreshing operation is available. Consequently, it is possible to compensate for deviations in offset voltage that are inherently caused by process deviations of MOS amplifiers, and to improve the precision of the output of the matched filter.Type: GrantFiled: April 2, 1997Date of Patent: September 28, 1999Assignee: Sharp Kabushiki KaishaInventors: Toshinobu Shibano, Kunihiko Iizuka
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Patent number: 5912584Abstract: In an analog signal processing device, an output signal and a reference level are compared by a comparator, and a result of comparison is filtered by a low-pass filter. By doing so, an adaptive control signal is generated so as to correspond to a background signal component having a low frequency, included in an input signal, and is negatively fed back to a signal processing unit. With this arrangement, the background signal component is compensated by the adaptive control signal having a frequency band sufficiently separate from a frequency band of a target signal component to be processed, the component being included in the input signal. As a result, a DC level of the output signal is stabilized at the reference level.Type: GrantFiled: June 6, 1997Date of Patent: June 15, 1999Assignee: Sharp Kabushiki KaishaInventor: Kunihiko Iizuka
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Patent number: 5900748Abstract: In a voltage comparator of the present invention, across a gate and a source of an amplifier transistor, a phase compensating capacitor and a first switch circuit are connected with each other in series, and a second switch circuit for short-circuiting the phase compensating capacitor is provided. The second switch circuit is turned on when the first switch circuit is turned off so as to (1) short-circuit the phase compensating capacitor and (2) discharge the phase compensating capacitor which has been charged while the first switch circuit was turned on. This permits to completely turn off the first switch circuit, and to prevent distortion of an output signal outputted from an output terminal, thereby preventing accumulation of unnecessary charges in the phase compensating capacitor.Type: GrantFiled: November 13, 1997Date of Patent: May 4, 1999Assignee: Sharp Kabushiki KaishaInventors: Ryuji Miyama, Kunihiko Iizuka, Kazuo Hashiguchi
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Patent number: 5878171Abstract: An encoding apparatus uses a vector quantization encoding method for encoding indexes of codewords, which supply a scalar quantized code of a maximum scalar product value of each code word in a code book, and its maximum scalar product value to a vector component of an input image inputted from an image sensor, so as to output the encoded indexes. A scalar product value calculating circuit in the encoding apparatus has scalar product value calculating sections, which are composed of an analog circuit having a code component capacitor corresponding to each code component, a differential amplifier and a feedback capacitor, corresponding to each codeword, and the scalar product values of the input vectors are calculated in parallel by the scalar product value calculating sections. In such a manner, when the analog calculation is made, the scale of the circuit can be decreased and the power consumption can be lowered.Type: GrantFiled: June 27, 1996Date of Patent: March 2, 1999Assignee: Sharp Kabushiki KaishaInventors: Masayuki Miyamoto, Kunihiko Iizuka, Hirofumi Matsui, Mitsuhiko Fujio
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Patent number: 5845016Abstract: An image compressing apparatus employs a mean-separated normalized vector quantization method according to which, with respect to vector components corresponding to input images inputted from image sensors via a plurality of lines, encodes and outputs a scalar-quantized code of a mean value, a scalar-quantized code of a maximum scalar product value with each code word in a code book, and an index of one of the code words which yields a maximum scalar product value. In this image compressing apparatus, when the maximum scalar product value is less than a predetermined threshold value, in accordance with judgement by a comparator circuit, an output selecting circuit stops outputting the codes of the maximum scalar product value and of the index, and outputs only the code of the mean value. Therefore, when the image is uniform with pixels varying little in their luminance levels in compression processing unit blocks, code data to be outputted are restricted so that only data of the mean value are outputted.Type: GrantFiled: June 27, 1996Date of Patent: December 1, 1998Assignee: Sharp Kabushiki KaishaInventors: Hirofumi Matsui, Kunihiko Iizuka, Masayuki Miyamoto, Mitsuhiko Fujio
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Patent number: 5818267Abstract: In respective comparators, a plurality of input voltages are compared with a comparison voltage that has been swept, and only the binary output of a D flipflop corresponding to the comparator that has exceeded the comparison voltage earliest is allowed to have "1", while the outputs corresponding to the rest of the comparators have "0". Therefore, it is possible to detect a maximum output by using the comparators of a normal CMOS construction and a binary-change detection means circuit constituted by logical circuits. Compared with the application of floating-gate MOS, this arrangement makes it possible to reduce costs, and also to easily carry out offset-voltage compensation for each comparator by using switched capacitors. As a result, in a maximum input detector which detects a maximum input from analog inputs through multiple channels by carrying out analog operations, it is possible to reduce costs, and also to improve detection precision.Type: GrantFiled: February 28, 1997Date of Patent: October 6, 1998Assignee: Sharp Kabushiki KaishaInventors: Mitsuhiko Fujio, Masayuki Miyamoto, Kunihiko Iizuka, Hirofumi Matsui
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Patent number: 5796647Abstract: An inner product calculation device for calculating an inner product of a coefficient vector including at least one first element with a positive sign and at least one second element with a negative sign and an input vector including elements corresponding to a plurality of input voltages.Type: GrantFiled: February 12, 1996Date of Patent: August 18, 1998Assignee: Sharp Kabushiki KaishaInventors: Kunihiko Iizuka, Mitsuhiko Fujio, Hirofumi Matsui, Masayuki Miyamoto
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Patent number: 5745010Abstract: An operational amplifier including reverse amplifiers interconnected in series in an odd number of stages not less than three, an element for feeding back an output from the reverse amplifier in the last stage to an input of the reverse amplifier in a first stage, and a feedback capacitance element provided across the input and output ends of at least one of the reverse amplifiers. The Miller effect makes the feedback current from the capacitance element appear as if it were increased by a factor of the amplification factor of a concerned inverter. Thus, the capacity of the capacitance element preventing the oscillation of the inverters can be reduced. As a result, the operational amplifier becomes highly responsive, and therefore, becomes operable for a high frequency signal.Type: GrantFiled: April 30, 1996Date of Patent: April 28, 1998Assignee: Sharp Kabushiki KaishaInventors: Masayuki Miyamoto, Kunihiko Iizuka
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Patent number: 5703503Abstract: A winner-take-all circuit for judging a channel receiving an analog signal having the largest or smallest value among multiple channels upon input of analog signals. Each basic circuit includes a detecting unit for comparing an input voltage with a reference voltage, and a feedback current generating unit for outputting a feedback current that determines a judging range in response to an output voltage from the detecting unit. The winner-take-all circuit also includes a tenth transistor serving as a common transistor to all the basic circuits. The tenth transistor secures, even when an input voltage is small, a current that should flow through a sixth transistor serially connected to the seventh transistor that determines an amount of a feedback current from the feedback current generating circuit.Type: GrantFiled: May 22, 1996Date of Patent: December 30, 1997Assignee: Sharp Kabushiki KaishaInventors: Masayuki Miyamoto, Kunihiko Iizuka, Mitsuhiko Fujio, Hirofumi Matsui