Patents by Inventor Kunihiro Fujii

Kunihiro Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100136505
    Abstract: An artificial teeth packaging container 1 includes an artificial teeth accommodating portion 7 for fixing a plurality of continuously arranged artificial teeth 2 detachably, and holding an arrangement position relation with an adjacent artificial teeth and an arrangement position relation with an upper or lower artificial molar teeth, in which the artificial teeth accommodating portion 7 covers the plurality of artificial teeth 2 from an occlusal plane in a state exposed around a cervical portion.
    Type: Application
    Filed: August 8, 2007
    Publication date: June 3, 2010
    Inventors: Hisashi Okada, Noriyuki Negoro, Kunihiro Fujii, Hirokazu Satoh
  • Publication number: 20100133124
    Abstract: An artificial teeth packaging container 1 including an accommodating member 7 having a plurality of accommodating pockets 10 to 13 in which artificial teeth 2 are inserted from opening portions 14 to 17 and accommodated therein, and a seal member 8 fixed to the accommodating member 7, for sealing the opening portions 14 to 17 of the plurality of pockets 10 to 13 accommodating the artificial teeth 2.
    Type: Application
    Filed: August 8, 2007
    Publication date: June 3, 2010
    Inventors: Hirokazu Satoh, Noriyuki Negoro, Kunihiro Fujii
  • Publication number: 20100119992
    Abstract: The present invention provides artificial teeth of upper and lower jaws pairing between the cusp tips and pits, allowing to operate the arrangement easily by clarifying the three-dimensional positional relation of cusp tips and pits to contact with each other in occlusion and the contact region. In an artificial tooth of a mandibular first premolar tooth having a buccal cusp tip, a lingual cusp tip, a mesial pit, and a distal pit, the azimuth originating from the distal pit, the ratio of distance to the mesial surface, distal surface, buccal surface, and the lingual surface, and the positional relation of the cusp tips and pits are set appropriately.
    Type: Application
    Filed: April 18, 2007
    Publication date: May 13, 2010
    Inventors: Hirokazu Satoh, Noriyuki Negoro, Kunihiro Fujii
  • Patent number: 7345362
    Abstract: An electronic component, in which a chip can be mounted on a certain predetermined place of the package at a high accuracy level, which package having a stepped level-difference in the inner wall of a cavity. The package is provided with a stepped level-difference in the inner wall surface, and an internal contact electrode formed on the upper surface of the stepped level-difference. At the bottom of the package is a shield electrode, on which a chip is mounted via an adhesion layer. The chip and the internal contact electrode are electrically connected by an interconnection wire. Location aligning for the chip and the interconnection wire, at least either one of these, is conducted by making use of a region, which is non-electrode portion, provided on the inner bottom surface of the package.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: March 18, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kozo Murakami, Kunihiro Fujii, Satoshi Matsuo
  • Publication number: 20070150300
    Abstract: A service recommendation system and a service recommendation method capable of improving the probability of the estimation of a user task and recommending a service depending on a user task can be provided. The user role obtaining unit 210 of the service recommendation server 100 obtains the role of a user, and the task estimating unit 207 estimates a user task from a task model associated with the obtained user role and stored in the task knowledge DB 103. The service knowledge retrieving unit 208 retrieves a service capable of assisting a user task obtained from the task estimating unit 207.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 28, 2007
    Applicant: NTT DoCoMo, Inc.
    Inventors: Yusuke Fukazawa, Takefumi Naganuma, Kunihiro Fujii, Shoji Kurakake
  • Publication number: 20070073665
    Abstract: Providing an information providing system and an information providing method capable of providing detail information required for a user to execute his/her scheduled activity smoothly.
    Type: Application
    Filed: September 28, 2006
    Publication date: March 29, 2007
    Applicant: NTT DoCoMo, Inc.
    Inventors: Takefumi Naganuma, Shoji Kurakake, Kunihiro Fujii, Yusuke Fukazawa
  • Patent number: 6984540
    Abstract: A surface acoustic wave device includes a piezoelectric substrate, a first interdigital transducer and a second interdigital transducer formed on the substrate so that the first and second interdigital transducers are opposed to each other. The substrate includes a doping region that is doped with a substance in at least one form selected from the group consisting of atoms, molecules and clusters in a surface between the first and second interdigital transducers.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: January 10, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitihiko Takase, Michio Okajima, Akihisa Yoshida, Kentaro Setsune, Kouzou Murakami, Kunihiro Fujii
  • Publication number: 20050036278
    Abstract: An electronic component, in which a chip can be mounted on a certain predetermined place of the package at a high accuracy level, which package having a stepped level-difference in the inner wall of a cavity. The package is provided with a stepped level-difference in the inner wall surface, and an internal contact electrode formed on the upper surface of the stepped level-difference. At the bottom of the package is a shield electrode, on which a chip is mounted via an adhesion layer. The chip and the internal contact electrode are electrically connected by an interconnection wire. Location aligning for the chip and the interconnection wire, at least either one of these, is conducted by making use of a region, which is non-electrode portion, provided on the inner bottom surface of the package.
    Type: Application
    Filed: September 2, 2004
    Publication date: February 17, 2005
    Inventors: Kozo Murakami, Kunihiro Fujii, Satoshi Matsuo
  • Patent number: 6848153
    Abstract: A method of manufacture of a surface acoustic wave device which includes a step of applying a photosensitive film resist on a substrate and forming a photosensitive film resist layer over at least a portion of a surface of the substrate; a step of forming acoustic absorbers only at the two sides orthogonal to the direction of the surface acoustic wave transmission; a step of placing in a package a surface acoustic wave element obtained by cutting and dividing the substrate and electrically connecting a connection electrode of the surface acoustic wave element with an external terminal of the package; and a step of sealing an opening of the package with a lid, wherein the main surface of the acoustic absorbers is formed parallel to the surface of the substrate.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: February 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeru Tsuzuki, Kunihiro Fujii, Masahiro Takada, Satoshi Matsuo, Takafumi Koga, Kozo Murakami
  • Patent number: 6804103
    Abstract: An electronic component, in which a chip can be mounted on a certain predetermined place of the package at a high accuracy level, which package having a stepped level-difference in the inner wall of a cavity. The package 13 is provided with a stepped level-difference 26 in the inner wall surface, and an internal contact electrode 14 formed on the upper surface of the stepped level-difference 26. At the bottom of the package 13 is a shield electrode 15, on which a chip 17 is mounted via an adhesion layer 16. The chip 17 and the internal contact electrode 14 are electrically connected by an interconnection wire 19. Location aligning for the chip 17 and the interconnection wire 19, at least either one of these, is conducted by making use of a region 18a, 18b, which is non-electrode portion, provided on the inner bottom surface of the package 13.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: October 12, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kozo Murakami, Kunihiro Fujii, Satoshi Matsuo
  • Publication number: 20040095038
    Abstract: A surface acoustic wave device includes a piezoelectric substrate, a first interdigital transducer and a second interdigital transducer formed on the substrate so that the first and second interdigital transducers are opposed to each other. The substrate includes a doping region that is doped with a substance in at least one form selected from the group consisting of atoms, molecules and clusters in a surface between the first and second interdigital transducers.
    Type: Application
    Filed: July 23, 2003
    Publication date: May 20, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Mitihiko Takase, Michio Okajima, Akihisa Yoshida, Kentaro Setsune, Kouzou Murakami, Kunihiro Fujii
  • Patent number: 6710682
    Abstract: A surface acoustic wave device of the present invention includes a piezoelectric substrate, a plurality of comb electrodes for exciting a surface acoustic wave, disposed on a principal plane of the piezoelectric substrate, a plurality of bumps disposed on the principal plane, and an insulating sheet disposed so as to be opposed to the principal plane, wherein the bumps and the comb electrodes are connected electrically to each other, and the bumps penetrate through the insulating sheet.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: March 23, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Onishi, Akihiro Nanba, Hiroki Sato, Katsunori Moritoki, Yoshihiro Bessho, Kunihiro Fujii, Kouzou Murakami
  • Patent number: 6680528
    Abstract: An electronic component having recesses on side faces of its package for housing an electric element therein. A metal layer that does not reach the bottom end of the package is formed on the surface of the recess. The metal layer has excellent wettability to a brazing material and helps extra material flow into the recess easily. In addition, the interface between the top end face of the recess and the side face is curved to make the brazing material flow into the recess easily. When the opening of the package is sealed with a lid using the brazing material, the extra brazing material flows into the recess. This prevents the brazing material from protruding outside of the package and thus improves dimensional accuracy of the electronic component. Therefore, mounting accuracy of the electronic component can be improved and short circuit can be prevented.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: January 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Matsuo, Kunihiro Fujii, Takafumi Koga, Kozo Murakami
  • Publication number: 20030127943
    Abstract: A SAW element (13) is formed of a piezoelectric substrate (14), on which are provided IDT electrodes (15), connection electrodes (16), underlying metal layers (17), and acoustic materials (18) placed on the underlying metal layers (17) and having surfaces parallel to the main surface of the piezoelectric substrate (14). The SAW element is mounted in a package (10), which is provided with external terminals (11) connected with the connection electrodes (16), and the package is hermetically scaled with a lid (20) to form a SAW device. When such a SAW element (13) is mounted faceup in a package (10) using a vacuum chuck (30), its piezoelectric substrate (14) can be protected against damage. When a SAW element (13) provided with bumps (23) on its connection electrodes (16) is mounted facedown in a package (10), the failure of electrical connections can be prevented.
    Type: Application
    Filed: December 10, 2002
    Publication date: July 10, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shigeru Tsuzuki, Kunihiro Fujii, Masahiro Takada, Satoshi Matsuo, Takafumi Koga, Kozo Murakami
  • Patent number: 6534901
    Abstract: A SAW element (13) is formed of a piezoelectric substrate (14), on which are provided IDT electrodes (15), connection electrodes (16), underlying metal layers (17), and acoustic materials (18) placed on the underlying metal layers (17) and having surfaces parallel to the main surface of the piezoelectric substrate (14). The SAW element is mounted in a package (10), which is provided with external terminals (11) connected with the connection electrodes (16), and the package is hermetically sealed with a lid (20) to form a SAW device. When such a SAW element (13) is mounted faceup in a package (10) using a vacuum chuck (30), its piezoelectric substrate (14) can be protected against damage. When a SAW element (13) provided with bumps (23) on its connection electrodes (16) is mounted facedown in a package (10), the failure of electrical connections can be prevented.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: March 18, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeru Tsuzuki, Kunihiro Fujii, Masahiro Takada, Satoshi Matsuo, Takafumi Koga, Kozo Murakami
  • Publication number: 20020101304
    Abstract: A surface acoustic wave device of the present invention includes a piezoelectric substrate, a plurality of comb electrodes for exciting a surface acoustic wave, disposed on a principal plane of the piezoelectric substrate, a plurality of bumps disposed on the principal plane, and an insulating sheet disposed so as to be opposed to the principal plane, wherein the bumps and the comb electrodes are connected electrically to each other, and the bumps penetrate through the insulating sheet.
    Type: Application
    Filed: October 3, 2001
    Publication date: August 1, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Onishi, Akihiro Nanba, Hiroki Sato, Katsunori Moritoki, Yoshihiro Bessho, Kunihiro Fujii, Kouzou Murakami
  • Publication number: 20020024130
    Abstract: An electronic component having recesses on side faces of its package for housing an electric element therein. A metal layer that does not reach the bottom end of the package is formed on the surface of the recess. The metal layer has excellent wettability to a brazing material and helps extra material flow into the recess easily. In addition, the interface between the top end face of the recess and the side face is curved to make the brazing material flow into the recess easily. When the opening of the package is sealed with a lid using the brazing material, the extra brazing material flows into the recess. This prevents the brazing material from protruding outside of the package and thus improves dimensional accuracy of the electronic component. Therefore, mounting accuracy of the electronic component can be improved and short circuit can be prevented.
    Type: Application
    Filed: July 3, 2001
    Publication date: February 28, 2002
    Inventors: Satoshi Matsuo, Kunihiro Fujii, Takafumi Koga, Kozo Murakami
  • Patent number: 6228766
    Abstract: Dopant impurities are ion implanted into active areas assigned to field effect transistors, and, thereafter, titanium silicide layers are formed from a titanium layer on the doped regions; when the dopant impurities are ion implanted into the doped regions, photo resist ion-implantation masks prevent a wide inactive area not assigned to any circuit component from the dopant impurities, and a thick titanium silicide is also grown on the wide inactive area; even when the titanium silicide layers are annealed with heat, the thick titanium silicide layer on the wide inactive area is not seriously coagulated, and an inter-level insulating layer is hardly separated from the titanium silicide layer on the wide inactive area.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: May 8, 2001
    Assignee: NEC Corporation
    Inventor: Kunihiro Fujii
  • Patent number: D616547
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: May 25, 2010
    Assignee: Kabushiki Kaisha Shofu
    Inventors: Hirokazu Satoh, Noriyuki Negoro, Kunihiro Fujii
  • Patent number: D616988
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Shofu
    Inventors: Hirokazu Satoh, Noriyuki Negoro, Kunihiro Fujii