Abstract: A semiconductor light-emitting element includes a light emission layer including a group III nitride semiconductor; an electron barrier layer disposed above the light emission layer and including a group III nitride semiconductor containing Al; and a p-type clad layer disposed above and in contact with the electron barrier layer, wherein the electron barrier layer and the p-type clad layer contain Mg as a dopant, and the p-type clad layer includes a high carbon concentration region containing carbon and a low carbon concentration region having a carbon concentration lower than a carbon concentration of the high carbon concentration region, in a stated order from an electron barrier layer side.

Abstract: A semiconductor light-emitting device includes: a first semiconductor layer containing a first conductivity type nitride semiconductor; an active layer containing a nitride semiconductor including Ga or In; an electron barrier layer containing a nitride semiconductor including at least Al, and being of a second conductivity type; and a second semiconductor layer containing a second conductivity type nitride semiconductor. The electron barrier layer includes a region where an Al composition ratio increases monotonically toward the second semiconductor layer. A maximum impurity concentration position of the second conductivity type in the electron barrier layer is located between an interface on an active layer side of the electron barrier layer and an intermediate position between a maximum Al composition ratio position of the electron barrier layer in the region and an interface on an active layer side of the electron barrier layer.

Abstract: A semiconductor light emitting element includes: a GaN substrate; a first semiconductor layer located above the GaN substrate and including a nitride semiconductor of a first conductivity type; an active layer located above the first semiconductor layer and including a nitride semiconductor including Ga or In; an electron barrier layer located above the active layer and including a nitride semiconductor including Al; and a second semiconductor layer located above the electron barrier layer and including a nitride semiconductor of a second conductivity type. The electron barrier layer includes: a first region having an Al composition ratio changing at a first change rate; and a second region having an Al composition ratio changing at a second change rate larger than the first change rate. In the first second regions, the Al composition ratio monotonically increases at the first change rate in the direction from the active layer toward second semiconductor layer.

Abstract: A semiconductor light emitting element includes: a GaN substrate; a first semiconductor layer located above the GaN substrate and including a nitride semiconductor of a first conductivity type; an active layer located above the first semiconductor layer and including a nitride semiconductor including Ga or In; an electron barrier layer located above the active layer and including a nitride semiconductor including Al; and a second semiconductor layer located above the electron barrier layer and including a nitride semiconductor of a second conductivity type. The electron barrier layer includes: a first region having an Al composition ratio changing at a first change rate; and a second region having an Al composition ratio changing at a second change rate larger than the first change rate. In the first second regions, the Al composition ratio monotonically increases at the first change rate in the direction from the active layer toward second semiconductor layer.

Abstract: A nitride semiconductor light-emitting element includes: n-side and p-side electrodes; n-type and p-type nitride semiconductor layers; and an active layer arranged between the n- and p-type nitride semiconductor layers. The p-type nitride semiconductor layer has a projection having a height of 30 nm to 50 nm. The projection is formed of a p-type nitride semiconductor including magnesium and silicon. The p-type nitride semiconductor has a silicon concentration of 1.0×1017 cm?3 to 6.0×1017 cm?3. The projection projects from the active layer toward the p-side electrode. On a plan view of the nitride semiconductor light-emitting element, the p-side electrode overlaps with the projection. The projection includes a dislocation. The projection is surrounded with a flat surface which is formed of the p-type nitride semiconductor. And the projection has a higher dislocation density than the flat surface.

Abstract: A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall.

Abstract: A nitride semiconductor light-emitting element uses a non-polar plane as its growing plane. A GaN/InGaN multi-quantum well active layer includes an Si-doped layer which is arranged in an InyGa1-yN (where 0<y<1) well layer, between the InyGa1-yN (where 0<y<1) well layer and a GaN barrier layer, or in a region of the GaN barrier layer that is located closer to the InyGa1-yN (where 0<y<1) well layer. A concentration of Si at one interface of the GaN barrier layer on a growing direction side is either zero or lower than a concentration of Si in the Si-doped layer.

Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

Abstract: A nitride semiconductor light-emitting element uses a non-polar plane as its growing plane. A GaN/InGaN multi-quantum well active layer includes an Si-doped layer which is arranged in an InyGa1-yN (where 0<y<1) well layer, between the InyGa1-yN (where 0<y<1) well layer and a GaN barrier layer, or in a region of the GaN barrier layer that is located closer to the InyGa1-yN (where 0<y<1) well layer. A concentration of Si at one interface of the GaN barrier layer on a growing direction side is either zero or lower than a concentration of Si in the Si-doped layer.

Abstract: A nitride semiconductor light-emitting element includes: n-side and p-side electrodes; n-type and p-type nitride semiconductor layers; and an active layer arranged between the n- and p-type nitride semiconductor layers. The p-type nitride semiconductor layer has a projection having a height of 30 nm to 50 nm. The projection is formed of a p-type nitride semiconductor including magnesium and silicon. The p-type nitride semiconductor has a silicon concentration of 1.0×1017 cm?3 to 6.0×1017 cm?3. The projection projects from the active layer toward the p-side electrode. On a plan view of the nitride semiconductor light-emitting element, the p-side electrode overlaps with the projection. The projection includes a dislocation. The projection is surrounded with a flat surface which is formed of the p-type nitride semiconductor. And the projection has a higher dislocation density than the flat surface.

Abstract: A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall.

Abstract: A semiconductor device 100 includes: a body region 105 of a first conductivity type placed on a principal surface of a substrate 101; a silicon carbide layer 102 including a drift region 107 of a second conductivity type; a channel layer 115 of the second conductivity type formed by silicon carbide and placed on the body region 105 and the drift region 107 on a surface of the silicon carbide layer 102; a gate insulating film 111 placed on the channel layer 115; a gate electrode 113 insulated from the silicon carbide layer 102 by the gate insulating film 111; a source electrode 116 provided on the silicon carbide layer 102; and a drain electrode 114 provided on a reverse surface of the substrate 101, wherein the source electrode 116 is in contact with the body region 105 and the channel layer 115; and a second conductivity type impurity concentration on a surface of the silicon carbide layer 102 that is in contact with the source electrode 116 is less than or equal to a second conductivity type impurity concen

Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

Abstract: A semiconductor chip of the present invention is a semiconductor device that includes a hexagonal semiconductor layer having anisotropic mechanical properties. A semiconductor chip (21), when viewed from a direction perpendicular to the semiconductor chip (21), has a rectangular shape that has a first side (1A) and a second side (1B) orthogonal to the first side (1A). The amount of thermal deformation along a direction in which the first side (1A) extends and the amount of thermal deformation along a direction in which the second side (1B) extends are substantially equal to each other.

Abstract: A semiconductor chip of the present invention is a semiconductor device that includes a hexagonal semiconductor layer having anisotropic mechanical properties. A semiconductor chip (21), when viewed from a direction perpendicular to the semiconductor chip (21), has a rectangular shape that has a first side (1A) and a second side (1B) orthogonal to the first side (1A). The amount of thermal deformation along a direction in which the first side (1A) extends and the amount of thermal deformation along a direction in which the second side (1B) extends are substantially equal to each other.

Abstract: A semiconductor device 100 includes: a body region 105 of a first conductivity type placed on a principal surface of a substrate 101; a silicon carbide layer 102 including a drift region 107 of a second conductivity type; a channel layer 115 of the second conductivity type formed by silicon carbide and placed on the body region 105 and the drift region 107 on a surface of the silicon carbide layer 102; a gate insulating film 111 placed on the channel layer 115; a gate electrode 113 insulated from the silicon carbide layer 102 by the gate insulating film 111; a source electrode 116 provided on the silicon carbide layer 102; and a drain electrode 114 provided on a reverse surface of the substrate 101, wherein the source electrode 116 is in contact with the body region 105 and the channel layer 115; and a second conductivity type impurity concentration on a surface of the silicon carbide layer 102 that is in contact with the source electrode 116 is less than or equal to a second conductivity type impurity concen

Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.