Patents by Inventor Kunimasa Takahashi
Kunimasa Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030227061Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.Type: ApplicationFiled: June 12, 2003Publication date: December 11, 2003Inventors: Toshiya Yokogawa, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Takeshi Uenoyama
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Patent number: 6654604Abstract: Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.Type: GrantFiled: November 20, 2001Date of Patent: November 25, 2003Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Masao Uchida, Makoto Kitabatake, Osamu Kusumoto
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Patent number: 6617653Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.Type: GrantFiled: January 30, 2002Date of Patent: September 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiya Yokogawa, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Takeshi Uenoyama
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Patent number: 6600203Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.Type: GrantFiled: April 22, 2002Date of Patent: July 29, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kunimasa Takahashi, Toshiya Yokogawa, Makoto Kitabatake, Masao Uchida, Osamu Kusumoto, Kenya Yamashita
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Patent number: 6580125Abstract: A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.Type: GrantFiled: August 15, 2002Date of Patent: June 17, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
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Publication number: 20030080384Abstract: A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat &dgr;-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.Type: ApplicationFiled: October 24, 2002Publication date: May 1, 2003Applicant: Matsushita Electric Industrial Co.., Ltd.Inventors: Kunimasa Takahashi, Masao Uchida, Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Kenya Yamashita, Ryoko Miyanaga
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Publication number: 20030020136Abstract: A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.Type: ApplicationFiled: August 15, 2002Publication date: January 30, 2003Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
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Publication number: 20030006415Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.Type: ApplicationFiled: February 26, 2002Publication date: January 9, 2003Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Makoto Kitabatake, Osamu Kusumoto, Takeshi Uenoyama, Koji Miyazaki
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Patent number: 6504176Abstract: There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively.Type: GrantFiled: April 3, 2001Date of Patent: January 7, 2003Assignee: Matshushita Electric Industrial Co., Ltd.Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi
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Publication number: 20020179909Abstract: A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.Type: ApplicationFiled: June 4, 2002Publication date: December 5, 2002Inventors: Masao Uchida, Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Kunimasa Takahashi, Ryoko Miyanaga, Kenya Yamashita
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Publication number: 20020158251Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.Type: ApplicationFiled: April 22, 2002Publication date: October 31, 2002Inventors: Kunimasa Takahashi, Toshiya Yokogawa, Makoto Kitabatake, Masao Uchida, Osamu Kusumoto, Kenya Yamashita
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Publication number: 20020060315Abstract: Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.Type: ApplicationFiled: November 20, 2001Publication date: May 23, 2002Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Masao Uchida, Makoto Kitabatake, Osamu Kusumoto
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Publication number: 20010053561Abstract: An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of a silicon carbide substrate is etched to form a concave portion. Then, a particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. Then, a gate electrode is formed on the oxide film.Type: ApplicationFiled: March 1, 2001Publication date: December 20, 2001Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi, Takeshi Uenoyama
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Publication number: 20010046757Abstract: A method for fabricating a semiconductor device that includes a semiconductor layer, containing Si and C, for its active region. Ions of a dopant are implanted into an SiC substrate a number of times, thereby forming a doped layer with multiple dopant concentration peaks in the substrate. Thereafter, the substrate is placed and annealed in a chamber with an etching gas (e.g., hydrogen gas) supplied thereto. In this manner, while the substrate is being annealed, the upper part of the doped layer is removed with the lower part thereof left. Accordingly, the dopant concentration at the surface of the lower doped layer can be easily controlled to such a value as required for forming a Schottky or ohmic electrode thereon. In addition, the upper doped layer with a lot of defects is removed, and therefore the surface region of the substrate can have its crystallinity improved.Type: ApplicationFiled: May 18, 2001Publication date: November 29, 2001Inventors: Kunimasa Takahashi, Makoto Kitabatake, Masao Uchida, Toshiya Yokogawa, Osamu Kusumoto
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Publication number: 20010038108Abstract: There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2eV, respectively.Type: ApplicationFiled: April 3, 2001Publication date: November 8, 2001Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi
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Patent number: 6306211Abstract: In a chamber, a substrate is mounted on a susceptor and then heated to an elevated temperature. Source and diluting gases are supplied into the chamber through source and diluting gas supply pipes provided with respective flow meters. In addition, a doping gas is also supplied through an additive gas supply pipe, which is provided with a pulse valve, and a gas inlet pipe into the chamber by repeatedly opening and closing the pulse valve. In this manner, a doped layer is grown epitaxially on the substrate. In this case, a pulsed flow of the doping gas is directly supplied through the pulse valve onto the substrate from the outlet port of a pressure reducer for a doping gas cylinder. As a result, a steeply rising dopant concentration profile appears in a transition region between the substrate and the doped layer, and the surface of the doped layer is planarized.Type: GrantFiled: March 10, 2000Date of Patent: October 23, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kunimasa Takahashi, Makoto Kitabatake, Masao Uchida, Toshiya Yokogawa
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Patent number: 6270573Abstract: A silicon carbide thin film is epitaxially grown by an MBE or the like method with silicon atoms 2 being maintained to be in excess of carbon atoms on a growth surface 1a of a silicon carbide crystal in a substrate 1. A silicon carbide substrate with a good crystallinity is thereby achieved at a low temperature with a good reproducibility. This crystal growth is possible at a low temperature of 1300° C. or lower, and the productions of a high-concentration doped film, a selectively grown film, and a grown film of a cubic silicon carbide on a hexagonal crystal are achieved. In crystallizing a cubic silicon carbide on a hexagonal crystal, the use of an off-cut surface inclined towards a <1{overscore (1)}00> direction is effective to prevent an occurrence of twin.Type: GrantFiled: April 26, 1999Date of Patent: August 7, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi
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Patent number: 6228720Abstract: An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of a silicon carbide substrate is etched to form a concave portion. Then, a particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. Then, a gate electrode is formed on the oxide film.Type: GrantFiled: February 18, 2000Date of Patent: May 8, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi, Takeshi Uenoyama
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Patent number: 4985184Abstract: Manufacture of granulated self-sintering carbonaceous pulverulent body suitable for precise complicated molding in high speed productivity is conducted in the presence of a wetting agent and a binding agent in the water-pulverulent mixture by using spray drying machine in the atmosphere of the hot air kept at a temperature up to 200.degree. C. optionally in admixture with superheated steam kept at a temperature up to 200.degree. C.Type: GrantFiled: September 19, 1988Date of Patent: January 15, 1991Assignee: Mitsubishi Petrochemical Company LimitedInventors: Kunimasa Takahashi, Takashi Kameda, Masato Yoshikawa, Teruo Teranishi
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Patent number: 4929404Abstract: A graphitic or carbonaceous molding comprising graphite powder and a mesophase-containing pitch is obtained by suspending graphite powder in a tar, heating the suspension while blowing an inert gas therein to form the mesophase-containing pitch on the graphite particles to obtain carbonaceous precursors and molding/carbonizing or graphitizing the carbonaceous precursors.Type: GrantFiled: May 17, 1988Date of Patent: May 29, 1990Assignee: Mitsubishi Petrochemical Company LimitedInventors: Kunimasa Takahashi, Takashi Kameda, Haruo Shibatani